JP2917384B2 - Information processing device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an information processing apparatus.

[Conventional technology]

Segmentation is one of the storage management methods of an information processing device. According to segmentation, storage is managed in units called segments. A segment is defined by a descriptor called a segment descriptor.

FIG. 3 shows an example of the segment descriptor. In this example, the segment descriptor is composed of three fields: flag, limit, and base. The flag section is provided with the attribute of the segment defined by the segment descriptor (readable, writable, executable, etc.). The reset section indicates the size of the segment. The base indicates the base address of the segment.

To access a segment, after loading a segment descriptor defining the segment into a register called a segment register, an address generated by an instruction (referred to as an execution address) is stored in the base of the segment descriptor loaded into the segment register. This is done by adding The relationship between the instruction and the operand at this time is shown in FIG.

The segment descriptor is stored in a segment managed by the control program, such as a parameter segment, an argument segment, and a linkage segment. The segment descriptor of each segment is stored in registers called parameter segment registers, argument segment registers, and linkage segment registers, and is managed by a control program.

In order to access an operand stored in a certain segment, the load pointer instruction loads a segment descriptor defining the segment and an address in the segment into a segment register and an address register, respectively.

FIG. 5 shows the outline of the operation of the load pointer instruction.

In the load pointer instruction, after an address is generated, the operand is directly obtained as an operand or a memory is accessed based on the address to obtain an operand (determined by an address modifier). The operand is divided into three fields called AR and SD as shown in the figure. The AR section is loaded into the address register as it is. The S and D parts are ID information of the segment descriptor. The S section indicates in which segment the segment descriptor is stored. The part D indicates the displacement address information in the segment. The segment descriptor specified by this ID information is loaded into the segment register.

[Problems to be solved by the invention]

As described above, in the conventional information processing apparatus, the load pointer instruction is an instruction that appears relatively frequently when accessing an operand stored in a different segment. Reading requires two memory accesses, and it is difficult to increase the speed.

Further, in a pipelined information processing apparatus, since the two memory accesses are not pipelined, there is a problem that the processing time is particularly long.

[Means for solving the problem]

An apparatus according to the present invention is an information processing apparatus that performs storage management by segmentation. The information processing apparatus includes: a predetermined instruction address information of a load pointer instruction in a history of past instructions; and a segment descriptor specified as an operand of the load pointer instruction.
History table means for storing a plurality of pairs of ID information; and in instruction prefetching, it is checked whether or not address information of a load pointer instruction to be prefetched is registered in the history table means. Means for reading ID information responding from the history table means in response to the identification of the registration, and reading of the segment descriptor read by the reading means.
Segment descriptor reading means for performing a segment descriptor reading operation according to the ID information.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a configuration diagram showing an embodiment of the information processing apparatus of the present invention, and FIG. 2 is a configuration diagram showing details of the address history table 106 of FIG.

The preceding controller 1 outputs a virtual address for reading an instruction, inputs a read instruction, outputs a virtual address for reading an operand of the input instruction, and reads an operand.

The instruction cache 2 inputs a virtual address for reading an instruction from the preceding control device 1 and outputs an instruction stored corresponding to the input virtual address.

The operand cache 3 inputs a virtual address for reading an operand from the preceding control device 1 and outputs an operand stored corresponding to the input virtual address to the preceding control device 1 and an operation execution device (not shown). .

 Next, the operation of this embodiment will be described.

The instruction prefetch IC 101 of the preceding control device 1 adds the base of the instruction segment stored in the instruction segment register 103 to the base of the instruction segment in the instruction virtual address register 105 for each instruction prefetch operation. The output of the instruction virtual address register 105 is sent to the instruction cache 2 as a virtual address for reading an instruction.
It is also sent to the address history table 106 of the preceding control device 1. It is assumed that no address corresponding to the input instruction prefetch address is recorded in the history table 106.

The instruction cache 2 converts the input instruction prefetch address by the address conversion mechanism 204 to generate a corresponding physical address. The instruction is read out by indexing the address part 205 and the data part 203 of the instruction cache based on the physical address. The read instruction is set in the instruction register 114 of the preceding control device 1.

The decode / control device 118 decodes the instruction set in the instruction register 114 to determine the type of the instruction. The address register file 116, the index register file 117, and the segment register file 11 are specified based on the specified bit position of the instruction set in the instruction register 114.
From 5, the contents of the address register, index register, and segment register are read. Instruction register 114
, And the contents of the address register, index register, and segment register are controlled by the decode / control device 118 through the registers 126, 1 via the selectors 119, 120, 121, 122, respectively.
24,125,123 are set respectively. Address adder 127
Calculates the operand address by adding the outputs of the registers 126, 124, 125, and 123, and the result is the virtual address register 12
Set to 8. The output of the virtual address register 128 is sent to the operand cache 3 as a virtual address for reading the operand.

The operand cache 3 converts the input operand address by the address conversion mechanism 301 to generate a corresponding physical address. Based on the physical address, the operand is read by indexing the address section 306 and the data section 303 of the operand cache. The read operands are stored in the address history table 106 of the operation execution device (not shown) and the preceding control device 1.
And sent to the selector 109.

If the instruction being processed is a load pointer instruction, the operand sent from the operand cache is the selector 109
Is set in the register 112 via The operand set in the register 112 is, as shown in FIG.
Section and D section. The segment descriptor of the segment in which the segment descriptor is stored is read out from the segment register file 115 based on the S portion, and is set in the register 123 via the selector 119. At the same time, the D section is set in the register 126 via the selector 122. At this time, '0' is set in the registers 124 and 125. Register 1
The values 23 to 126 are added by the address adder 127 and sent to the operand cache 3 as a virtual address. The segment descriptor stored at the address corresponding to the virtual address is read and sent to the operation execution device.

The arithmetic execution device stores the AR portion of the operand read first and the segment descriptor read next in the address register file 116 and the segment register file 115, and ends the processing of the load pointer instruction (the path is not shown).

FIG. 2 shows the address history table in FIG.
106 details are shown. History table 106 is CAM
It has a structure. In this embodiment, a four-word fully associative configuration is used, but the number of words is not limited.
Also, a set associative configuration may be used.

In the tag section 11 of the history table 106, the address where the instruction of the load pointer is stored is set as the execution history. This address is the address calculation IC110
Is output to the tag unit 11 when the decode / control device 118 detects the load pointer instruction. The data section stores the ID information S and D sections of the operands of the load pointer instruction sent by the operand cache 3.
It is paired with the address information stored in the tag unit 11. The address calculation IC 110 is used for a relative branch instruction or the like, and holds the address where the instruction set in the instruction register 114 is stored. Since the instruction register 114 is set for each instruction word, the increment is 1 address. It is performed one by one.

When the load pointer instruction at the same address is processed again, it is used as a history stored in the history table 106. When the instruction read virtual address is sent from the register 105, it is compared with the value of the tag unit 11 by the comparison circuit 13. If a match is found here, the data portion paired with the matched tag portion 11 is set in the register 107 via the selector 15. Information indicating a match is generated by the OR gate 14 and set in the flip-flop 108.

The values of the register 107 and the flip-flop 108 are set in the register 112 and the flip-flop 113, respectively. Load pointer instruction is stored in instruction register 11 from instruction cache 2.
4, the decoder / control device 118 determines that the S and D portions of the load pointer instruction have been read out to the register 112 based on the value of the flip-flop 113, reads the operand, and reads the segment descriptor. Reading can be performed continuously.

〔The invention's effect〕

As described above, the present invention uses the history table means for storing the address at which the load pointer instruction is stored in the tag section and storing the ID information of the segment descriptor of the instruction in the data, using the history table means. By obtaining ID information from the data section output obtained by indexing the history table means according to prefetching,
Since instruction prefetching and ID information reading can be performed in parallel, the operand and segment descriptor can be read continuously compared to the process of reading the segment descriptor based on the ID information included in the operand. It has the effect of reducing it.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram of an information processing apparatus showing one embodiment of the present invention, FIG. 2 is a schematic block diagram of a history buffer, FIG. 3 is a diagram showing the relationship between segments and segment descriptors, and FIG. FIG. 5 is a diagram showing a relationship between a segment and an operand in a storage management system by segmentation, and FIG. 5 is a diagram showing processing of a load pointer instruction. 1 ... preceding control device, 2 ... instruction cache, 3 ... operand cache.

Claims (1)

(57) [Claims] 1. An information processing apparatus for performing storage management by segmentation, comprising: a predetermined segment descriptor in a history of past instructions and instruction address information of an instruction to load an address in a segment into a segment register and an address register, respectively. History table means for storing a plurality of pairs of ID information of a segment descriptor designated as an operand of the instruction; and in instruction prefetching, address information of the instruction to be prefetched is registered in the history table means. Means for examining whether or not the instruction has been registered and reading ID information responding from the history table means in response to the registration of the instruction; and an ID of the segment descriptor read by the reading means.
An information processing apparatus comprising: a segment descriptor reading unit that performs a segment descriptor reading operation according to information.