JPH07271580A - Data processor provided with branching destination prediction processing function - Google Patents

Abstract

PURPOSE:To accurately predict a branching destination instruction (or an address) by the execution of a branching instruction and to perform the high- speed processing of the branching instruction. CONSTITUTION:This processor is provided with a first instruction memory 101 for holding history information which is the record of the executed results of branching in the past, branching destination addresses and information required for predicting the branching instruction of a branching destination instruction code and a second instruction memory 104 provided with an instruction code. The instruction of a branching destination is predicted from the history information in the execution of the branching instruction and pre-fetching is performed from the branching destination address and the instruction code in advance. Thus, the branching destination instruction is predicted at a high speed with sure prediction accuracy and the processing of the branching instruction is performed at a high speed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing device or a computer for processing data based on instructions, and more particularly to speeding up the execution processing of branch instructions.

[0002]

2. Description of the Related Art When a branch instruction is executed in the instruction execution / arithmetic processing of a conventional data processor or computer (hereinafter referred to as a data processor), it takes several cycles to fetch the branch destination instruction.

In particular, the conditional branch instruction determines the condition from the operation result and determines whether to execute the branch destination address or the next instruction following the branch instruction. The loss of the number of cycles is large.

In order to reduce the loss of the above machine cycle, branch prediction is performed.

That is, the branch destination where the branch will be executed is predicted before the accurate execution result of the branch instruction is known,
The predicted instruction is speculatively executed.

Such a branch prediction method is based on the "Alternative Implementation of Two-Level Adaptive" of 19th-ISCA.
As described in "Branch Prediction", etc., a static method that determines the prediction when it is found to be a branch instruction by the instruction code, and the branch destination address at the previous execution time, taken / not taken information other than the instruction code. There is a dynamic method that saves the history, etc. and determines the prediction from that information.

The static method takes when the displacement is negative.
It is a method that predicts n and predicts not taken when the displacement is positive. This is BTFN (Backward Taken For
wardNot-taken).

FIG. 2 shows a dynamic method.

This is a method of reducing a branch penalty by a method (H32 / 200) which has a branch prediction buffer having a branch target address and a branch target instruction code and issues the branch target address and the branch target instruction code at high speed.

FIG. 3 shows a method for saving the history of execution results of conditional branches, predicting the branch destination based on the information, and increasing the accuracy of the branch destination (DEC Alpha, etc.).

[0011]

According to the above-mentioned respective prior arts, there is a problem that the prediction of the conditional branch is missed because there is no history of the execution result of the conditional branch in the branch prediction buffer.

Further, in the case of holding the history of execution results of conditional branch, since there is no branch destination address and branch destination code,
Even if the prediction of the branch target is successful, the address calculation of the branch target and the fetch of the branch target instruction cannot be performed quickly, and there is a problem that the machine cycle penalty due to the branch processing increases.

An object of the present invention is to accurately predict branch destinations,
Moreover, it is to provide a data processing device with a small branch processing penalty.

[0014]

The features of the present invention for achieving the above object are that a branch destination address, an instruction code string including the branch destination instruction, and a branch instruction corresponding to the instruction address of the branch instruction. This is achieved by having a first instruction memory that also has the execution history of.

[0015]

According to the history, by registering the execution result of the past branch instruction, and by dynamically predicting the execution of the branch when the next branch instruction is executed, the branch prediction becomes easy to hit. By registering the branch destination address and the branch destination instruction code, when the branch instruction is executed next time, without actually calculating the branch destination address or fetching the branch destination instruction code from the second instruction memory, It can be issued directly from the first instruction memory, reducing the branch penalty when the prediction hits.

[0016]

FIG. 1 shows a first embodiment to which the present invention is applied.

The computer system of the present invention comprises a first instruction memory 101 holding a branch instruction history (also referred to as branch execution history information) 101a, a branch destination address 101b, and a branch destination instruction code 101c, an arithmetic unit 102, and a main memory 1.
03, second instruction memory 1 holding instruction code 104a
04 and.

Although all instruction codes are held in the main memory 103, commonly used instruction codes are copied to the first instruction memory 101 or the second instruction memory 104 such as cache memory which can be accessed faster. .

The arithmetic unit 102 fetches an instruction code from the first instruction memory 101, the second instruction memory 104, or the main memory 103, performs an operation according to the instruction code, and outputs the operation result to the main memory 103 or the data cache memory. Etc.

FIG. 4 is a diagram showing FIG. 1 in detail.

The arithmetic unit 102 comprises an arithmetic unit 402 and a data memory 403.

The arithmetic unit 402 sends the instruction address 402a to the first instruction memory 101 and the second instruction memory 104, and the instruction code 101f and the dynamic branch destination prediction information (branch instruction history or branch execution) from the first instruction memory 101. (Also referred to as history information) 101d, a branch destination address 101e, and an instruction code 404a from the second instruction memory 104.

The arithmetic unit 402 also sends the registration information 402b to the first instruction memory.

Further, the arithmetic unit 402 is provided with a data memory 4
The data address 402c is sent to 03, and the data 405 is accessed.

The data memory 403 outputs data corresponding to the data address 402c received from the arithmetic unit 402. Further, the data not held in the data memory is accessed from the main memory 103 using the data path 410.

The second instruction memory 104 receives the instruction address 402a from the arithmetic unit 402 and outputs the instruction code 404a to the arithmetic unit 402. Further, the instruction code not held in the second instruction memory is accessed from the main memory 103 via the data bus 410.

The operation unit 402 predicts that the instruction code corresponding to the instruction address 402a issued to the first instruction memory 101 includes a branch instruction, and the branch instruction is taken to the branch destination by the dynamic branch prediction information 101d. If so, the branch destination address 101e and the branch destination instruction code 101f registered in the first instruction memory 101 are accessed to advance the execution of the branch destination instruction.

The presence of the branch destination address 101e enables immediate fetching of the branch destination instruction, and the presence of the branch destination instruction code 101f enables immediate issue of the branch destination instruction.

If the dynamic branch prediction information 101d predicts that the instruction indicated by the instruction address 402a is not a branch instruction or will not be taken to the branch destination, the second instruction memory 10
The next instruction code 404a is accessed from 4 and executed.

If no instruction code exists in the second instruction memory 104, the instruction code is accessed from the main memory 103 via the data bus 410.

Further, the arithmetic unit 402 executes a branch instruction, determines whether or not to change the registered content of the first instruction memory 101 based on the execution result, and uses the registration information 402b to determine the first instruction memory 101. Change the registered contents of.

When the arithmetic unit 402 executes an instruction to access the main memory, the arithmetic unit 402 further stores the data address 40.
2c is output to the data memory 403 and the data 403a is accessed. At this time, if there is no data to be accessed in the data memory 403, the data is fetched from the main memory 103 via the data bus 410.

FIG. 19 shows the case of a single branch. 4 indicated by the address of the program counter (hereinafter referred to as PC)
When the instruction includes a branch instruction and the branch destination address is t, the operation of the embodiment shown in FIG. 4 will be described with reference to the time chart of FIG.

() Represents the instruction code indicated by the address written therein.

When the instruction address 402a is a PC,
The first instruction memory is hit, and the dynamic branch prediction information 101d for the next cycle becomes information indicating a prediction that is taken (hereinafter referred to as taken prediction).

Further, t is output to the branch destination address 101e, and the branch destination instruction (t) is output to the instruction code 101f.

The second instruction memory has an instruction address 402a.
Since the corresponding instruction code 404a appears after two cycles of, the branch destination instruction can be obtained earlier by introducing the first instruction memory.

In other words, if the first instruction memory does not have a branch destination instruction, it takes 1 to obtain the branch destination instruction address by subtracting the first instruction memory from the instruction address 402a.
This is because it takes two cycles to obtain the branch destination instruction by drawing the second instruction memory with the branch destination instruction address output in the cycle 402a.

FIG. 22 shows a case of continuous branch in which there is another branch at the branch destination t1 of the branch in the PC and further branch at the branch destination t2.

FIG. 23 shows the operation when the embodiment of FIG. 4 executes the case of FIG.

Due to the effect of the first instruction memory, the instruction address 4
The branch destination address can be sequentially output to 02a in one cycle, and the branch destination instruction can be fetched in the instruction code 101f every cycle, and the speed can be increased.

FIG. 5 is a configuration example of the first instruction memory 101 of FIG.

The first instruction memory 101 has an address tag 5
01, history 502, branch destination address 503, branch destination instruction code 504, registration control circuit 505, comparator 506, and dynamic prediction control circuit 507.

The address tag 501, the history 502, the branch destination address 503, and the branch destination instruction code 504 are an associative memory which is drawn by the lower 402ab of the instruction address.
The address tag 501 is input at 402aa and outputs 501a, the history 502 is input at 510 and outputs 502a, the branch destination address 503 is input at 505a and outputs 101e, and the branch destination instruction code 504 is input at 505a and 101f. Is output. The registration control circuit 505 receives the registration information 402b, the history 510, and the hit information 507a, and outputs a new history 510, a branch destination address, and a branch destination instruction code 505a.

Comparator 506 is used for instruction address upper 402
Upon receiving aa and the address tag 501a, a hit 506a is output. The dynamic prediction control circuit 507 receives the instruction address upper 402aa, the hit 506a, and the history 502a,
The dynamic branch prediction information 101d and the hit information 507a are output.

In this embodiment, the case where four consecutive instructions are fetched simultaneously for one instruction address is shown.
Although there are four branch destination instruction codes 504, it is possible to fetch more instructions.

Next, the operation will be described.

Lower several bits 40 of instruction address 402a
The address tag 501 is pulled with 2ab.

Since the upper bit of the registered address is contained in the address tag 501, if this is compared with the instruction address upper 402aa by the comparator 506,
It is determined whether or not the information corresponding to the instruction address currently to be executed is stored in the first instruction memory, and it is output as the hit 506a.

From this hit 506a, history 502a, instruction address 402a, etc., the dynamic prediction control circuit 507
Determines whether to be taken or not taken. The dynamic branch prediction information 101d includes information such as dynamic prediction / not predicted, taken prediction / not taken prediction, and the like. The hit information 507a includes information of dynamic prediction / non-prediction.

Further, the registration control circuit 505 includes a calculation unit 40.
2 from the registration information 402b and the dynamic prediction control circuit 507
Upon receiving the hit information 507a from, the history 502 is updated and other fields are registered.

FIG. 6 shows an example of the configuration of the arithmetic unit 402 shown in FIG.

The operation unit 402 is an instruction scheduler 60.
1, instruction address unit 602, register file 6
03, an arithmetic unit 604, a static prediction control circuit 605, a condition determination unit 606, and a registration information generation unit 607.

The instruction scheduler 601 includes the instruction code 101f from the first instruction memory 101, the dynamic branch prediction information 101d, and the instruction code 40 from the second instruction memory 104.
Receiving 4a, instruction address unit 602, arithmetic unit 6
04, the static prediction control circuit 605, the registration information generation unit 607, etc., the instruction code 601a is distributed to the instruction address unit 6
02 is the instruction code 60 from the instruction scheduler 601.
1a, static prediction result 60 from static prediction control circuit 605
5a, the condition determination result 606a from the condition determination unit 606,
From the instruction address 402a, etc., the branch destination address 602a
Is generated and sent to the registration information generation unit 607, the stream address 602b is generated, and the branch position 601b is sent to the registration information generation unit 607.

The register file 603 is stored in the arithmetic units 604 and 61 through the instruction address units 602 and 610.
1, the register values are exchanged via the data memories 403 and 405.

The computing unit 604 is the instruction scheduler 601.
From the register file 603 to 611, the register value is read through the register files 603 to 611, the operation result is sent to the data memory 403 as a data address via 402c, and the operation result is sent to the condition determining unit 606 via 402c.

The static prediction control circuit 605 receives the instruction code 601a from the instruction scheduler 601 and the dynamic branch prediction information 101d from the dynamic prediction control circuit 507 of FIG.
The method of static prediction is determined, and the static prediction result 605a is sent to the instruction address unit 602 and the registration information generation unit 607.

The condition judging unit 606 judges a condition such as a conditional branch from the calculation result of the calculator 604, and the condition judgment result 6
06a is an instruction address unit 602, a registration information generation unit
Send to 607.

The registration information generation unit 607 includes an instruction code 601a from the instruction scheduler 601, a branch position 601b from the instruction address unit 602, and a static prediction control circuit.
Static prediction result 605a from 605, branch destination address 602a from instruction address unit 602, condition determination unit 6
The condition determination result 606a from 06 is received, and the registration information 402b is sent to the registration control circuit 505 in FIG.

FIG. 18 is a flow chart for executing a branch instruction incorporating dynamic prediction.

First, in the instruction fetch cycle, the first instruction memory is searched to determine whether or not the corresponding branch instruction is registered in the first instruction memory. If registered, it becomes a hit, static prediction is suppressed, and taken prediction or not taken prediction is performed according to dynamic prediction. And
When the conditional branch instruction is actually executed and the result of the condition judgment is made, it is determined whether the prediction is correct or incorrect, and if the prediction is incorrect, the correct instruction address is reissued.
A process to cancel the pipeline is required.

When (5) is actually taken in the taken prediction and (6) is actually not taken in the taken prediction, the branch destination instruction in the pipeline is canceled and the instruction on the side where the branch is not skipped is deleted. Start over. (7) is not ta
(8) is not ta if it is actually not taken in the ken prediction.
If it is actually taken by ken prediction, the instruction in the pipeline where the branch was not taken is canceled and the branch destination instruction is redone.

When the first instruction memory is missed, the static prediction is performed to determine the prediction from the instruction code.

Static prediction is also taken prediction or not taken
There are predictions, and there are hits and misses in each, and there are 4 states as in the case of dynamic prediction. (1) (2) (3) (4)
Is.

Next, the operation of the embodiment shown in FIG. 6 will be described.

The instruction scheduler 601 receives the instruction code 101f from the first instruction memory and the instruction code 404a from the second instruction memory and outputs the instruction code 601a which is about to be executed at present. Static predictive control circuit 605
Is the dynamic branch prediction information 10 from the first instruction memory 101.
Suppress static prediction when 1d indicates to make dynamic prediction. When the dynamic branch prediction information 101d from the first instruction memory 101 indicates that dynamic prediction is not performed, static prediction is performed and a static prediction result 605a indicating taken prediction and not taken prediction is output.

The instruction address unit 602 decodes the branch instruction from the instruction code 601a, calculates the address according to the instruction format, and generates the branch destination address 602a. Based on the static prediction result 605a from the static prediction control circuit 605, the predicted instruction address is output to the stream address 602b.

When the conditional branch is not predicted, the conditional decision result 606a from the conditional decision 606 of the conditional branch is performed.
Is used to output the return instruction address from the incorrect prediction to the stream address 602b.

Further, when the branch is not made, the instruction address 4
The stream address 602b is generated by a procedure such as incrementing 02a to generate a new instruction address.

For the instruction address 402a, when the dynamic branch prediction information 101d from the first instruction memory predicts taken, the branch destination address 101e from the first instruction memory is selected, and otherwise, from the instruction address unit 602. It is generated by selecting the stream address 602b.

Further, the instruction address unit 602 generates a return address and writes it in the register file 603 through 610 when it is a branch instruction used for calling a subroutine or the like and for saving the return address.

In the calculator 604, the instruction code 601a is A
When the operation instruction is a DD instruction or the like, the register value is read from the register file 603 through 611, the corresponding operation is performed, and the register file 6 is returned through 611.
Write the resulting value to 03. When the instruction code 601a is an instruction for memory address access,
A data address is generated and output to the data memory at 402c.

Data from or to the data memory is exchanged through 403a.

The registration information generator 607 determines whether the condition determination result 6
06a, branch destination address 602a, static prediction result 605
The registration information 402b is generated from a, the instruction code 601a, the branch position 601b, etc., and sent to the first instruction memory 101.

FIG. 15 shows the details of the instruction scheduler 601 which is changed by introducing the first instruction memory 101.

The instruction scheduler 601 is the selector 160.
1, an instruction buffer 1602, a conflict determination 1603, and an instruction buffer control 1604.

The selector 1602 has the first instruction memory 10
The instruction code 101f from 1 and the instruction code 404a from the second instruction memory are selected by the dynamic branch prediction information 101d, and the execution instruction code 1601a is output.

The execution instruction code 1601a becomes the instruction code 101f from the first instruction memory when the dynamic branch prediction information 101d predicts taken, and the instruction from the second instruction memory when predicting not taken. Code 404a
Becomes The instruction buffer 1602 is a buffer for storing the fetched instruction code for a while, and the instruction buffer control 1
Controlled by the instruction buffer control signal 1604a from 604, the instruction code 601a is issued to the arithmetic unit.

The conflict determination 1603 is executed by the instruction buffer 160.
The instruction issue number 1603a is calculated by determining register conflict or the like from the instruction code 601a from 2.

The instruction buffer control 1604 determines the contention determination 1
The instruction buffer control signal 1604a is sent to the instruction buffer from the instruction issue number 1603a from the 603.
Control the 1602.

FIG. 7 is a diagram showing a second embodiment of the present invention.

Different instruction addresses 702a and stream addresses 702d are simultaneously sent from the operation unit 702 to the first instruction memory and the second instruction memory, and different instruction codes 101 are sent from the first instruction memory and the second instruction memory, respectively.
f, 404a is received.

Branch destination address 101 from the first instruction memory
e. The instruction on the side where the branch has not been skipped from the second instruction memory at the same time as receiving the branch destination instruction code 101f
Can receive 404a.

The operation of FIG. 7 will be described with a time chart.

FIG. 21 shows the operation of the embodiment of FIG. 7 in the case of the single branch of FIG.

When the instruction address 402a is a PC,
The first instruction memory is hit, and the dynamic branch prediction information 101d of the next cycle points to the taken prediction. At this time, in the next cycle, the first instruction memory is drawn at the instruction address 402a that is the branch destination address t, and the second instruction memory is drawn at the stream address 702d that is the PC + 16 address created by the instruction address unit. be able to. Therefore, not only the branch destination instruction (t) of the instruction code 101f, but also the instruction (PC +
16) can also be fetched with the instruction code 404a, and the pipeline can be immediately switched when the prediction is wrong, and the performance is improved.

FIG. 24 shows the operation of the embodiment of FIG. 7 in the case of continuous branching of FIG.

In FIG. 24, the instruction code 1 is assigned to each branch destination instruction.
In addition to fetching to 01f, it is possible to fetch all the instructions on the side where the branch of each branch instruction has not been skipped with the instruction code 404a, and the penalty of the branch instruction can be suppressed to the utmost limit.

FIG. 8 is a diagram showing the configuration of the arithmetic unit 702 of FIG. As the stream address 702d to be output to the second instruction memory 104, PC + 16 made of the instruction address unit, which is not the branch destination address 101e from the first instruction memory 101, is output. Other than this point, it is the same as FIG.

The instruction scheduler 601 in the arithmetic unit 702 shown in FIG. 8 can be configured as shown in FIG. 15 just as in the first embodiment.

However, taking advantage of the feature that the instruction on the side where the branch is not skipped can be fetched by the instruction code 404a, the operation unit is configured as shown in FIG. 17, and the instruction scheduler 1801 included therein is shown in FIG. Can be configured as follows.

FIG. 17 shows the configuration of the arithmetic unit 702. Explaining only the parts different from FIG. 8, the instruction scheduler 1801 uses the instruction code 10 from the first instruction memory 101.
1f, instruction code 404 from second instruction memory 404a
a, static prediction result 605 from the static prediction control circuit 605
a, the condition determination result 606a from the condition determination unit 606, and the dynamic branch prediction information 101d are received, and the instruction code 601a is output.

In FIG. 16, the instruction schedule 1801
Is taken side instruction buffer 1701, not taken side instruction buffer 1702, selector 1703, conflict determination 160
3 and instruction buffer control 1604. taken
The side instruction buffer 1701 receives the instruction code 101f from the first instruction buffer 101 and receives the instruction buffer control 16f.
Controlled by the taken side instruction buffer control signal 1604a from 04, the taken side instruction 1701a is output.

The not taken side instruction buffer 1702 receives the instruction code 404a from the second instruction buffer 404, and is controlled by the not taken side instruction buffer control signal 1604b from the instruction buffer control 1604.
The n-side instruction 1702a is output.

The selector 1703 controls the instruction issue control 170.
4 is selected by the select signal 1704a from
The instruction code 606a is issued to the arithmetic unit. The instruction issuance control 1704 includes a static prediction result 605 a from the static prediction control circuit 605 and a condition determination result 60 from the condition determination unit 606.
6a outputs a select signal 1704a. The conflict determination 1603 is the instruction code 6 from the instruction buffer 1602.
The number of issued commands is 1 based on the judgment of register conflict from 01a.
603a is calculated. The instruction buffer control 1604 uses the instruction issue count 1603a from the conflict determination 1603 to take
The en side instruction buffer control signal 1604a is sent to the taken side instruction buffer 1701, and the not taken side instruction buffer control signal 1604b is sent to the not taken side instruction buffer 170.
2 to control each instruction buffer.

Next, the operation of FIG. 16 will be described.

The taken-side instruction buffer 1701 has a branch
This is a buffer that stores the instruction code ahead from the branch destination address when taken, and is the instruction buffer 170 on the not taken side.
Reference numeral 2 is a buffer for storing the previous instruction code from the subsequent address of the branch when the branch is not taken.

The instruction issue control 1704 selects the select signal 1704a so that the side 1701a is selected when the static prediction result 605a from the static prediction control circuit 605 indicates the taken prediction and the side 1702a is selected when the static prediction result 605a indicates the not taken prediction. To control.

Then, as a result of branch execution, the condition judging unit 6
When the condition judgment result 606a from 06 indicates a misprediction, and if the prediction is wrong in the taken prediction, 1702 on the not taken side
a side, not taken If the prediction is wrong, 170 on the taken side
The select signal 1704a is controlled so that the 1a side is selected.

As a result, the instruction code on the misprediction side can be issued immediately, and it is not necessary to start over from the instruction fetch, so the branch penalty can be further reduced. This fetches the taken instruction of the branch from the first instruction memory, and at the same time not the branch of the second instruction memory.
This is the effect of being able to fetch the instruction on the taken side.

FIG. 9 is a diagram showing the structure of the first instruction memory 101 of FIG. The address 402aa for pulling the first instruction memory 101 and the address tag 501 to be registered in the first instruction memory 101 are not the entire upper order of the instruction address but a part thereof. As a result, the address tag 501,
The number of bits of the comparator 906 can be reduced, and the hardware can be reduced. However, if there is a branch instruction with a large displacement exceeding the bit being compared by the comparator, the dynamic prediction information will give incorrect information. In order to correct this, the function of address check 1008 is added in FIG.

FIG. 10 is a diagram showing the configuration of the arithmetic unit 702 of FIG. In FIG. 10, address check 1 from FIG.
It has a configuration in which 008 is newly added. The address check 1008 receives the instruction code 601a from the instruction scheduler 601, the branch destination address 602a and the stream address 702d from the instruction address unit 1002, and outputs the misprediction 1008a to the instruction address unit 10
Take out to 02. The address check 1008 compares the true branch destination address 1002a generated by the instruction address unit 1002 with the possibly erroneous instruction address 402a fetched from the first instruction memory bit by bit. The instruction address unit 1002 receives the correct instruction address due to the miss signal 1008a.
1002a is issued and the branch destination instruction is fetched. If they match, the dynamic prediction can be used to execute the branch instruction in one cycle.

By this address check 1008, a register-relative branch or the like can be registered in the first instruction memory to perform dynamic prediction control. If the registers required for address calculation have been rewritten, it is predicted that a mismatch has occurred in the address check 1008, and the prediction error 1008a.
Therefore, the branch destination address for which the actual address has been calculated should be adopted.

The effect of this embodiment is that the hardware of the first instruction memory can be reduced.

FIG. 11 is a diagram showing a fourth embodiment of the present invention.

The arithmetic unit 102 comprises an arithmetic unit 1102. The first instruction memory 101 receives the instruction address 402a from the arithmetic unit 1102, and the arithmetic unit 1102 receives the instruction code.
101f, dynamic prediction information 101d, branch destination address 101e
To send. Also, the registration information 402b from the arithmetic unit 1102 is received. The operation unit 1102 receives the instruction code 101f, the dynamic prediction information 101d, and the branch destination address 101e from the first instruction memory 101, sends the instruction address 402a to the first instruction memory 101, and the second instruction memory 110.
Command address / data address 1102c to 4,
Second instruction memory 1104 and instruction code / data 1105
To exchange.

The second instruction memory 104 receives the instruction address / data address 1102a from the arithmetic unit 402 and exchanges the instruction code / data 1105 with the arithmetic unit 402. In addition, the main memory 103 and the data bus 41
Through 0, exchange of instruction code / data.

FIG. 12 is a diagram showing the configuration of the arithmetic unit 1102 of FIG. The instruction scheduler 1201 is shown in FIG.
The instruction code 101f from the first instruction memory 101, the dynamic prediction information 101d, and the instruction code fetched from the second instruction memory 1104 using the instruction code / data 1105 are received, and the instruction address unit 602, the arithmetic unit 604, The instruction code 601a is distributed to the static prediction control circuit 605, the registration information generation unit 607, and the like. The instruction address / data address 1102 selects and outputs the stream address 602a, the instruction address 402a, and the calculation result 604a from the calculator 604.

The embodiment shown in FIG. 11 corresponds to the second embodiment shown in FIG.
In this embodiment, the second instruction memory 104 and the data memory 403 are merged into one. Therefore, the address to be sent to the second instruction memory 1104 which also serves as the instruction / data is such that the instruction address 402a from the instruction address unit 602 and the data address 604a from the arithmetic unit 604 in FIG. 12 are selected and output. The data 1105 exchanged with the second instruction memory 1104 is the second
The instruction memory 1104 and the instruction scheduler 1201, the second instruction memory 1104 and the register file 603 are connected to each other so that the instruction and the data serve as a memory.

The effect of this embodiment is that the amount of memory is saved by placing the data memory on the second instruction memory, the efficiency of use of the second instruction memory is increased, and a system with good cost performance can be provided. is there.

FIG. 13 is a diagram showing the configuration of the first instruction memory 101 of FIG. The lower part of the instruction address 402ab is composed of an address tag 501, a history 502, a branch destination address 503, a branch destination instruction code 504, and an R field 1302 indicating a branch used for a subroutine return. The return address stack is
It is written with the registration information 505a from the registration control circuit 505 and outputs the return address 1301a. R field 1
302 is registration information 505a from the registration control circuit 505.
And the select signal 1302a is output. The branch destination address 101e is the return destination address stack 13
Return address 1301 from 01 and branch destination address 5
503a from 03 is selected by the select signal 1302a and generated.

In this embodiment, in order to speed up the branch instruction used for the subroutine return, the subroutine return address generated at the time of the subroutine call is stacked on the return address stack and the return address is taken out from the stack at the time of the return. It is an example in which the present invention is applied to a prediction buffer that can quickly obtain a branch destination address of an instruction. For example, as shown in FIG. 22, the branch of the subroutine call and the branch of the subroutine return are respectively
It is a BL instruction that inserts register number 2 and a BV instruction that has a return value of 0 in register number 2.

The first instruction memory has a bit field R1302 representing a subroutine return. When this bit is set, the branch destination address 101e is set to the return address 1301a output from the return address stack 1301. By doing so, the branch destination address 101e can be obtained in one cycle.

FIG. 14 is a diagram showing the configuration of the arithmetic unit 702 shown in FIG. As shown in FIG. 14, whether or not the prediction is successful is the same as in the example of FIG.
Judgment at 08. 14 is different from FIG. 10 in that the return address 1402c is added to the signal from the instruction address unit 1402 to the registration information generating unit 1407, and the instruction address unit 1 is added to the registration information 402b in the first instruction memory 101.
The only difference is that the return address 1402c created in 402 is newly included.

According to this embodiment, there is an effect of improving the performance that the branch of the subroutine return can be executed in one cycle.

[0116]

The effect of the first embodiment is that the history, the branch destination address, and the branch destination instruction code are combined to enable more reliable high-speed prediction.

The effect of the second embodiment is to reduce the penalty when the prediction is wrong. The effect of the third embodiment is that the hardware of the first instruction memory can be reduced.

The effect of the fourth embodiment is that the amount of memory is saved by placing the data memory on the second instruction memory, the efficiency of use of the second instruction memory is increased, and a system with good cost performance can be provided. is there.

The fifth embodiment has the effect of improving the performance in which the branch of the subroutine return can be executed in one cycle.

[Brief description of drawings]

FIG. 1 shows a first embodiment to which the present invention is applied.

FIG. 2 is a conventional example of a branch prediction buffer having a branch destination address and a branch destination instruction code.

FIG. 3 is a conventional example of a branch prediction buffer that performs prediction based on a history of execution results of conditional branches.

FIG. 4 is a detail of FIG.

5 is a configuration example of a first instruction memory 101 of FIG.

6 is a configuration example of a calculation unit 402 in FIG.

FIG. 7 is a second embodiment of the present invention.

8 is a configuration of a calculation unit 702 in FIG.

9 is a configuration of the first instruction memory 101 of FIG. 7. FIG.

10 is a configuration of a calculation unit 702 in FIG.

FIG. 11 is a fourth embodiment of the present invention.

12 is a configuration of a calculation unit 1102 in FIG.

13 is a configuration of the first instruction memory 101 of FIG.

14 is a configuration of a calculation unit 702 in FIG.

15 is a configuration of a scheduler 601 of FIG.

16 is a configuration of a scheduler 1801 of FIG.

17 is a configuration of a calculation unit 702 of FIG.

FIG. 18 is a flowchart of branch instruction execution that incorporates dynamic prediction.

FIG. 19: Single branch case.

20 is the operation of FIG. 4 in the case of the single branch of FIG.

FIG. 21 is the operation of FIG. 7 in the case of the single branch of FIG.

FIG. 22: Case of continuous bifurcation.

FIG. 23 is the operation of FIG. 4 in the case of continuous branching of FIG. 22.

24 is the operation of FIG. 7 in the case of continuous branching of FIG.

[Explanation of symbols]

101 ... First instruction memory, 101a ... History, 101b ...
Branch destination address, 101c ... Branch destination instruction code, 102 ... Arithmetic unit, 103 ... Main memory, 104 ... Second instruction memory, 104a ... Instruction code.

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Akira Okuno 7-1, 1-1 Omika-cho, Hitachi-shi, Ibaraki Hitachi Ltd. Hitachi Research Laboratory (72) Inventor Kenji Saito 1 Horiyamashita, Hadano-shi, Kanagawa General Manager Computer Division, Hiritsu Manufacturing Co., Ltd.

Claims (9)

[Claims] According to each branch instruction, branch execution history information indicating a result of branching by execution of a branch instruction up to that point, a branch destination address designated by the branch instruction, and a branch destination instruction code are provided. A first instruction memory unit for holding, a second instruction memory unit for holding an instruction code of an instruction, and an instruction address for executing data processing in the second instruction memory unit.
Output to the instruction memory, fetch the instruction code of the instruction corresponding to the instruction address from the second instruction memory, determine whether the fetched instruction code is the branch instruction, and execute the branch execution if it is the branch instruction. A branch destination including a calculation unit that fetches a branch destination instruction based on history information using the branch destination address and the instruction code of the branch destination, and processes data based on the fetched instruction code. A data processing device having a prediction processing function. 2. Branch execution history information indicating the result of branching by the execution of the branch instruction up to that point, branch destination address specified by the branch instruction, and branch destination instruction code according to each branch instruction. And a second instruction memory unit for holding the instruction code of the instruction, a data memory unit for holding the data, and an instruction address for executing the processing of the data.
Output to the instruction memory, fetch the instruction code of the instruction corresponding to the instruction address from the second instruction memory, determine whether the fetched instruction code is the branch instruction, and execute the branch execution if it is the branch instruction. A branch destination instruction based on history information is fetched using the branch destination address and the instruction code of the branch destination, and based on the fetched instruction code, data specified by the instruction code is read from the data memory, A data processing device having a branch destination prediction processing function, comprising: an arithmetic unit for processing data. 3. The arithmetic unit according to claim 1 or 2, wherein the arithmetic operation unit detects a match between a branch destination address subjected to branch processing by the branch instruction and a predicted branch destination address predicted based on the branch execution history information, A data processing apparatus having a branch destination prediction processing function, comprising a history information updating unit for updating the branch execution history information. 4. A main storage unit for holding instructions and data, branch execution history information showing a result of branching by execution of a branch instruction up to that point, and the branch instruction specified by the branch instruction. A first instruction memory unit for holding a branch destination address and an instruction code for the branch destination, a second instruction memory unit for holding an instruction code of an instruction, and an instruction address for executing data processing. And fetches the instruction code of the instruction corresponding to the instruction address from the second instruction memory, determines whether the fetched instruction code is the branch instruction, and if it is the branch instruction, the branch execution history information. A branch destination instruction based on the above-mentioned branch destination address and the above-mentioned branch destination instruction code, and processes data based on the fetched instruction code. A data processing system having a branch destination prediction processing function, comprising: a processor unit including an arithmetic unit; and a bus unit connecting the main storage unit and the processor unit. 5. A main storage unit for holding instructions and data, branch execution history information indicating a result of branching by the execution of the branch instruction up to that point, and the branch instruction specified by the branch instruction. A first instruction memory unit for holding a branch destination address and a branch destination instruction code,
A second instruction memory unit for holding the instruction code of the instruction, a data memory unit for holding the data, and an instruction address for executing the processing of the data, output to the second instruction memory,
The instruction code of the instruction corresponding to the instruction address is fetched from the second instruction memory, it is determined whether the fetched instruction code is the branch instruction, and if it is the branch instruction, the branch destination based on the branch execution history information. An operation unit that fetches an instruction using the branch destination address and the branch destination instruction code, reads the data specified by the instruction code from the data memory based on the fetched instruction code, and processes the data. A data processing system having a branch destination prediction processing function, comprising: a processor unit consisting of; and a bus unit connecting the main memory unit and the processor unit. 6. The arithmetic unit according to claim 4 or 5, wherein the arithmetic operation unit detects a match between a branch destination address subjected to branch processing by the branch instruction and a predicted branch destination address predicted based on the branch execution history information, A data processing system having a branch destination prediction processing function, comprising a history information updating unit for updating the branch execution history information. 7. The arithmetic unit according to claim 4, wherein if the instruction code corresponding to the instruction address output from the arithmetic unit is not in the second instruction memory unit, the arithmetic unit is the main memory. Data access system having a branch destination prediction processing function, wherein the instruction address is accessed from the second section to the second instruction memory section. 8. The arithmetic unit according to claim 4, wherein if the instruction code corresponding to the instruction address output from the arithmetic unit is not in the first instruction memory unit, the arithmetic unit is the main memory. Data access system having a branch destination prediction processing function, wherein the instruction address is accessed from the first section to the first instruction memory section. 9. The branch destination prediction process according to claim 4, wherein the arithmetic unit accesses the first instruction memory unit and the second instruction memory unit in parallel. Data processing system with functions.