JP3014701B2 - Information processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to an information processing apparatus of a virtual memory system operable in an access register mode, which aims at increasing the operation speed of an MVCL instruction, and is provided with a first operand and a second operand of an MVCL instruction. When the register number for specifying the operand address is not 0, the contents of the access register corresponding to the register number are selected. On the other hand, when the register number for specifying the operand address is 0, Means for setting the data as all "0", and the first means selected or set by the means.
Means for comparing the data relating to the operand and the data relating to the second operand, and controlling whether or not to check for a destructive overlap of the addresses of the first operand and the second operand using the result of the comparison. Constitute.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus having a virtual storage device composed of a plurality of address spaces, and more particularly to an inspection of destructive overlap when data is moved in a real space, and in particular, to an MVCL.
The present invention relates to an information processing apparatus capable of controlling at a high speed whether or not to perform an overlap check on an address specified by a first operand and a second operand when executing an instruction.

[Related Art] A demand for an information processing apparatus in recent years is an increase in the amount of data to be processed. This is particularly significant in database systems. Along with this demand, there is a demand for an architecture capable of directly accessing data in a plurality of address spaces from a user program beyond the limit of the address space in the conventional virtual storage device. Appeared.

That is, in an information processing apparatus having a conventional virtual memory, only accessing data in a single address space specified by a control register is permitted. Therefore, in order to refer to data in a plurality of address spaces, it is necessary to replace the contents of the control register, which is under the control of the operating system. Under such control, a user program was not allowed to directly process data over a plurality of address spaces. However, the demand for the expansion of the virtual memory space has increased, and it is necessary to perform control to allow a user program to access a plurality of address spaces having different base register numbers beyond the range of a given address space. It happened.

As a mechanism for this, the following method can be considered. In other words, a segment table is prepared for each of a plurality of address spaces used by the user, and a plurality of segment table origins (STOs), which are pointers to the table, are provided. The base register number used in the access indicates which one to use. Determined by the contents of the access register indexed by As a method of the determination, an access list in the real storage space is indexed by the contents of the access register, and which STO is used to access the virtual storage space using the base register number is specified. The access by the access register is described in Nikkei Computer, September 12, 1988, 105
Details are provided on pages 109-109.

The base register number designation portion is located at a limited bit position of the instruction word, and the content of the register selected based on the content becomes the input of the addition circuit for generating the effective address.

The state of the information processing device that performs address conversion using such an access register is called an access register mode, and the access register mode is defined by a specific bit in a program status word (PSW).

MVCL (MOVE
CHARACTER LONG) instruction. This is an RR format instruction that moves data at an address in the real space corresponding to the information given by the second operand of the instruction word to an address in the real space corresponding to the information given by the first operand. (MOVE) This instruction is used when a relatively large amount of data needs to be moved in the real space.

As a well-known method for moving data of the MVCL instruction to the programmer, it is usual to read one byte at a time,
Although the specification is such that data is written one byte at a time at the target address, in practice, there is a relationship between the speed and the bus width for reading data from the memory at one time. The data to be written is not always one byte at a time.

Therefore, when the first operand address and the second operand address are close to each other, destructive overlapping of data may occur.

Normally, destructive overlapping can be avoided by limiting one access to the length of the difference between the first operand data and the second operand data.

On the other hand, in the access register mode described above,
Access to a plurality of address spaces is permitted, but at this time, since access register conversion is performed, different addresses in the real space are given even if the effective address values of the operands of the instruction word match.

Therefore, conversely, even when the effective addresses are different, destructive competition in the real space may occur.

Therefore, when executing an instruction, it is necessary to check whether or not destructive overlap occurs.

[Problems to be Solved by the Invention] In the access register mode in which access register conversion is performed as described above, the first operand and the second operand of the MVCL instruction are access registers corresponding to register numbers designating respective operand addresses. Should be present in the address space indicated by the contents of the access register, the destructive overlap check is performed only when the contents of the access registers corresponding to the first operand and the second operand match. If the register number specifying the operand address is zero, the specified operand must exist in the primary virtual storage space, and the processing is performed with the contents of the access registers compared being all zero.

In order to realize such processing in a conventional information processing device, a register number is checked in a microprogram executing an MVCL instruction, an access register is selected based on the result, a comparison of selected contents is checked, and the result is checked. , It is necessary to control the selection of a branch to determine whether or not to perform a destructive overlap inspection by the control.

FIG. 5 is a flowchart showing a microprogram routine for processing such a conventional MVCL instruction.

FIG. 6 shows the control shown by the above flow chart as a pipeline time chart.

Hereinafter, the operation will be described based on FIG. 5 and FIG.

(A) Check the register number of the first operand of the MVCL instruction shown in FIG. 6 (corresponding to step 16 in FIG. 5). The check is performed in the B cycle of the pipeline. It is determined whether or not all are 0 in the W cycle (the determination result is STATUS).

In the case of all 0s, since the designated operand exists in the primary virtual storage space, the processing is performed assuming that the contents of the access register to be compared are all zeros (fifth order).
Figure flowchart, step 24).

(B) FIG. 6 shows a dummy stage.

(C) Flow of FIG. 6 (corresponding to step 16 in FIG. 5) If the register number is not 0 as a result of the stage check, the contents of the access register corresponding to the number are stored in the arithmetic unit (E unit). Send to

(D) In FIG. 6, the same processing as in FIG. 6 is performed for the second operand.

(E) In the flow of FIG. 6, the contents of the two access registers are compared by the E unit. The comparison corresponds to step 19 in the flowchart of FIG.

Thereafter, data transfer is started (step 20 in the flowchart of FIG. 5).

If the access register numbers match in step 19 of the flowchart of FIG. 5, a check is made for a destructive overlap (steps 21 to 23 in the flowchart of FIG. 5).

As can be seen from the above description, the conventional method based on microprogram control involves a large number of processing steps, so that the number of processing cycles is large and high-speed processing cannot be expected.

In view of such a conventional problem, the present invention dynamically converts an operand address of an instruction using an access register provided in a CPU and an access list on a main memory in an access register mode, thereby achieving a plurality of operations. It is an object of the present invention to provide means capable of executing an MVCL instruction at a high speed in an information processing apparatus of a virtual memory system configured so as to be able to refer to data in the address space.

[Means for Solving the Problems] According to the present invention, the above-mentioned object is achieved by the means described in the claims.

That is, a virtual memory configured to be able to refer to data in a plurality of address spaces by dynamically converting an operand address of an instruction using an access list provided in a CPU and an access list on a main memory. Operand of an instruction for moving data at an address in a real space corresponding to information given by a second operand to an address in a real space corresponding to information given by a second operand When the register number for designating the operand address is not 0 for each of the second operand and the second operand, the contents of the access register corresponding to the corresponding register number are selected, while the register number for designating the operand address is 0. , A first circuit for setting data as all “0”; And data of the first operand is selected or set by the first circuit, a second circuit for comparing the data of the second operand, the second
When a result indicating that both data match is obtained by the circuit of (1), the first operand address and the second operand
A third circuit for controlling whether or not to check for overlap with an operand address.

[Operation] In the present invention, in the access register mode in which the access register conversion is performed, the first operand and the second operand of the MVCL instruction are the addresses indicated by the contents of the access register corresponding to the register numbers specifying the respective operand addresses. Since it should exist in the space, the destructive overlap check is performed only when the contents of the access registers corresponding to the first operand and the second operand match. If the register number specifying the operand address is zero, the specified operand must exist in the primary virtual storage space, and the processing is performed with the contents of the access registers compared being all zero.

In the conventional processing method, a register number is checked in a microprogram that executes an MVCL instruction, an access register is selected based on the result, a comparison of selected contents is checked,
Although the branch selection as to whether or not to perform the destructive overlap inspection based on the results is performed, in the present invention, since these are configured to be performed by hardware, high-speed processing can be expected.

Embodiment FIG. 1 is a block diagram showing an embodiment of the present invention, wherein 1 is a latch for holding a base register number of B cycle, 2 is a decoder, and 3-1 to 3-n are AND gates, respectively. , Is an access register, 5 is a latch, 6 is an arithmetic unit, 7 is a latch for holding an address comparison result (exclusive OR (EOR) result) by the arithmetic unit, 8
Reference numerals -1 to 8-n and 9 denote OR gates, 10 denotes an AND gate, 11 denotes a latch, and 12 denotes a destructive overlap condition detection circuit.

FIG. 2 is a time chart showing an example of the operation of the above embodiment.

In FIG. 1, the base register number is set in the latch 1 in the B cycle, the decoding result and the B-μ-TA which is the access register read signal in the B cycle are set.
The corresponding access register is selected by an AND condition with the G signal, and its contents are temporarily held in the latch 5 and then sent to the arithmetic unit 6 (E unit of the CPU).

The above operation is performed as shown in the time chart of FIG.
This is performed on the first operand and the second operand of the MVCL instruction, and both data are compared by the arithmetic unit 6 (this comparison is actually obtained as an exclusive OR of both data, and the result is compared with the comparison result. Become). Then, the comparison result is converged by the OR circuits 8-1 to 8-n and 9 and held in the latch 11. And gate
The circuit consisting of 10 is a circuit that creates the timing for setting data in the latch 11.

The output of the OR gate 9 is "0" (this means that the exclusive OR of the contents of the access registers corresponding to the operands 1 and 2 is all "0"). . While this is held in the latch 11, the INH-DISABLE-OVERLAP-CHK as shown in FIG.
The signal is up, and in this state DISABLE-OVERLAP-CH
Even if the K signal is detected, the data is moved as usual.

FIG. 3 is a block diagram showing an example of the configuration of the destructive overlap condition detection circuit 12, and 13 is a B-latch (B-latch).
LATCH), 14 is a C-latch, 15 is a CO-latch, and 16-1 to 16-3 are AND gates.

In the figure, B-LATCH is (OP1 address) ≧
When the condition of (OP2 address) is detected, the latch holds the result (OP1 represents operand 1 and OP2 represents operand 2. The same applies hereinafter).

The C-LATCH is a latch that holds the result when a condition of [MIN (OP1 length, OP2 length) + OP2 address]> OP1 address is detected.

Further, CO-LATCH is a latch that holds the result when a condition of [MIN (OP1 length, OP2 length) + OP2 address]> OP2 address is detected. When this latch is set, operand 2 is This indicates that wraparound is not performed.

Each of the above conditions is detected by looking at the carry of a special adder.

The AND condition of the AND gate 16-1 in FIG.
B-LATCH * C-LATCH, the AND condition of the AND gate 16-2 is B-LATCH * ▲ ▼, and the AND condition of the AND gate 16-3 is C-LATC
H If one of these conditions is satisfied, a destructive overlap condition is established.

FIG. 4 is a diagram for explaining conditions under which such destructive overlap (overlap) occurs.
(A) is the state of data overlap when the condition of B-LATCH * C-LATCH is satisfied, (b) is B-LATCH * ▲
The state of data overlap when the condition of ▼ is satisfied, and the state of data overlap when the condition of C-LATCH * ▲ is satisfied.

In the figure, OP1A indicates the start address of operand 1 and OP2A indicates the start address of operand 2.

[Effects of the Invention] As described above, according to the present invention, in the access register mode, the operand address of an instruction is dynamically converted using an access register provided in the CPU and an access list on main memory. , An information processing apparatus of a virtual memory system configured to be able to refer to data in a plurality of address spaces, and determining whether to perform a check for destructive overlap of data when executing an MVCL instruction. There is an advantage that it is possible to realize an information processing apparatus capable of quickly obtaining a result, and to thereby speed up processing of an MVCL instruction.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a time chart showing the operation of the embodiment, FIG. 3 is a block diagram showing an example of the configuration of a destructive overlap condition detection circuit,
FIG. 4 is a diagram for explaining conditions that cause destructive overlap, FIG. 5 is a flowchart showing a microprogram routine for processing a conventional MVCL instruction, and FIG. 6 is a pipeline diagram showing control of processing of a conventional MVCL instruction. It is a time chart. 1, 5, 7, 11 ... latch, 2 ... decoder, 3-1 to 3-n,
16-1 to 16-3,10 ... AND gate, 4 ... access register, 6 ... arithmetic unit, 8-1 to 8-n, 9 ... OR gate, 12 ... destructive overlap condition detection circuit, 13
…… B-latch, 14 …… C-latch, 15 …… CO-latch, 16 to 24 …… Operation on the flowchart

──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-59-42684 (JP, A) JP-A-1-305429 (JP, A) JP-A-59-33551 (JP, A) (58) Field (Int.Cl. ⁷ , DB name) G06F 9/30-9/355 G06F 12/08-12/12

Claims (1)

(57) [Claims] The present invention is configured such that data in a plurality of address spaces can be referred to by dynamically converting an operand address of an instruction using an access register provided in a CPU and an access list on a main memory. A virtual memory type information processing device, comprising: an instruction word for moving data at an address in a real space corresponding to information given by a second operand to an address in a real space corresponding to information given by a first operand; When the register number for designating the operand address is not 0 for each of the first and second operands, the contents of the access register corresponding to the corresponding register number are selected, while the register for designating the operand address is selected. A first circuit for setting data as all "0" when the number is 0; A second circuit for comparing the data relating to the first operand selected or set by the first circuit with the data relating to the second operand; and determining that the two data are identical by the second circuit. And a third circuit for controlling whether or not to check whether the first operand address overlaps the second operand address using the result when the result is obtained. .