JPS61296448A - Data writing control system for electronic computer - Google Patents

Abstract

PURPOSE:To improve the reduction of processing in a bus cycle by forming both address and data comparators, a writing data queue and a control circuit and reducing the number of bus accesses to write data. CONSTITUTION:An operand writing address Adr calculated by an operand address calculating part 1 is sent to the writing data queue 7 together with data length dl and an address comparing result Z and set up in a blank queue. The coincidence/discrepancy between reading and writing operands is discriminated in each 16 bits corresponding to the external data bus width by a reading operand register 4 and a data comparator 5. The compared result C is inputted to a control circuit 6 through a signal line 109. On the basis of the control information of the writing data queue 7 and the data comparing result, the control circuit 6 controls V bits indicating the existence of data in the queue 7.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a circuit configuration of an electronic computer, and more particularly to a write control method in an electronic computer with a pipeline control structure that reads, decodes, and executes instructions in parallel.

(Prior Art) Conventionally, in order to improve processing speed, minicomputers and large computers have been divided into functional units that can operate in parallel to read and decode instructions, read and execute operands, and A so-called pipeline method has been adopted, which executes a series of processes such as storing results and storing results in a flow-like manner. In this case, the processing time for each unit can be shorter than when it is not divided into functional units, and each unit can be operated in parallel, so high-speed processing can be achieved. .

On the other hand, even in microprocessors, which have developed rapidly with the development of LSI technology, improvements in the degree of integration have made it possible to incorporate the above-mentioned pipeline method. High-speed switching was possible.

(Problems to be Solved by the Invention) As mentioned above, microprocessors have been made faster by LSI technology, but as the speed of microprocessors increases, the bus cycles decrease relatively, and the performance of microprocessors decreases depending on the bus speed. The problem of being suppressed and becoming entrenched has become apparent. In order to increase the bus speed and maximize the performance of the microprocessor, K must add expensive hardware such as cache memory.

SUMMARY OF THE INVENTION An object of the present invention is to provide a data one-input control method for an electronic computer, which eliminates the above-mentioned drawbacks by reducing the number of bus accesses and writing operations, and which is able to counteract the deterioration in processing caused by bus cycles. It is about providing.

(Means for Solving the Problems) The data writing control method for an electronic computer according to the present invention is adopted in a pipeline structure in which at least instruction decoding, operand access, and instruction execution are performed in parallel. , a data comparison circuit, a write data queue, and a control circuit.

The address comparison circuit is for detecting a match between the read address and write address of the operand in one instruction, and the data comparison circuit is for comparing the read operand and the write operand in the instruction using the data width of the external data bus. It is for the purpose of

The write data queue contains the write operand and its address, word length, and control information.

The control circuit is for controlling control information in the write data queue.

In the above configuration, if the word length of the write operand is equal to or greater than the width of the external data bus, and there is a portion that matches the read operand, writing of the portion to the memory can be omitted. It is composed of

(Example) Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a data write control method for an electronic computer according to the present invention.

In this embodiment, a 16-bit external data bus is provided, and 3
A microprocessor with a 2-bit internal data processing unit is assumed. In FIG. 1, 1 is an operand address calculation unit, 2 is a read read address register, 5 is an address comparator, 4-digit read operand axis, 5 is a data comparator, 6 is a control circuit, 7 is an honorable data queue, 1
0 is an instruction decoding section, and 20 is an instruction execution section.

In FIG. 1, the write data queue 7 consists of two registers with the same structure, each containing control information (Z
, V), write address (Adr), write data length (
dl) and Sogodani data (Data).

Z on signal line 10B and in write data queue T
is information indicating that the addresses of the read operand and write operand match, and is transmitted from the instruction decoder 10 together with the pledge address and the draft data length.

The I3 number V on the A3 line 104 and the ILE number V in the write data queue 7 is information indicating that write data is contained.1 Normally, when a write operand is transmitted from the instruction execution unit 10, it becomes %1 #, and the memory When writing to %0IV(l is completed).

The operand address calculation section 1 is an operand address calculation means placed in the instruction decoding section 10, and the read/write address of the operand is calculated here before the instruction execution section 20 executes the instruction. The read address of the operand is temporarily latched in the read address register 2, and when calculating the write address of the operand, it is determined by the address comparator 3 whether or not it matches the write address.

The operand address calculation unit 1 calculates the operand write address based on the data length dl and address comparison result 2.
It is also sent to the write data queue 7, and set in an empty register in the write data queue 7.

The data register of write data queue 1 consists of 16 bits, and when the data length is 32 bits, data is set in two registers of write data queue 7 with 16 bits.

A read operand register 4 and a data comparator 5 determine whether the read and write operands match. Note that data comparison is performed in units of 16 bits, which corresponds to the external data bus width. The comparison result C is input to the control circuit 6 via the signal line 109. Based on the control information of the write data queue 1 and the data comparison result, the control circuit 6 controls the V bit indicating the presence or absence of data in the write data queue 7.

FIG. 2 shows that the control circuit 6 inputs the control information (Z) and data length (dA') of the write data queue 7, as well as the data comparator 5.
FIG. 3 is an explanatory diagram showing how to control the V bit based on the comparison result C from the above.

In Table 1, 2 is information indicating a match between the operand addresses; 10I indicates a mismatch, and %11 indicates a match. di is information representing the data length of the operand; %OOl represents 1 byte, %01l represents 2 bytes, %11 N represents 4 bytes.

C is information representing a match between operands in units of 2 bytes, %Ol represents a mismatch, and 111 represents a match.

Vl and V2 are information indicating whether data exists in the write data queue 7, 101 represents no data, and %11 represents data present.

Referring to the second (!I), for example, if the addresses match and the operand data length is 32 bits (Z=1idl
=11), the upper 16 bits and lower 16 bits of the read and write operands are both equal (C=
In case 11), the V bit remains at %a1, so no commitment to memory is made. If only the lower 16 bits are equal (C=01), only the V bit (Vl) of the register that should be used first is %11, and the V bit of the register that should be used next (V2)
becomes %Ol. If only the upper 16 bits are equal, the V bit (
Vl) becomes %Ol, which becomes the V bit 754'l# of the register that should be used next.

In such a case, the write operation to the memory is performed only once. If the upper 16 bits and lower 16 bits are not equal, both bits Vl and V2 will be 1,
Write operations to memory are performed only twice.

In this example, no change is made to the data length dl. This is because by looking at the lower 1 bit of dl, it can be easily determined whether 1 byte or 2 bytes are to be accessed.

(Effects of the Invention) As explained above, the present invention compares the data at the time of reading and the data at the time of writing when performing a read/write operation on operands having the same address, and changes are made. By actually writing only the parts that were there υ,
In particular, a microgrocer whose internal processing data width and external bus data width are different (for example, internal processing is performed with a 32-bit data width, and the external data bus is 8-bit or 16-bit data width)
This has the effect of reducing the number of bus accesses and increasing processing speed in (bit processors).

[Brief explanation of the drawing]

FIG. 1 shows a data document 1 of an electronic computer according to the present invention.
Operand address adjustment unit 2...Read address register 3...Address comparator 411...Read operand register 5...Data comparator 6.m-control circuit 1...Write data queue 10...・Instruction decoding unit 20...Instruction execution unit 101-103---Bus 104-110...Signal line patent application NEC Corporation representative Patent attorney Hisashi Inoro Figure 2

Claims (1)

[Claims] A data write control method for an electronic computer with a pipeline structure in which at least instruction decoding, operand access, and instruction execution are performed in parallel, and for detecting a match between a read address and a write address of an operand in one instruction. an address comparison circuit; and a data comparison circuit for comparing a read operand and a write operand in the instruction using the data width of an external data bus;
A write data queue including a write operand, its address, word length, and control information, and a control circuit for controlling the control information in the write data queue, and the word length of the write operand is greater than or equal to the width of an external data bus. 1. A data write control method for an electronic computer, characterized in that, if there is a portion that matches a read operand, writing of said portion to memory can be omitted.