JPH0348931A - Mvcl instruction control system - Google Patents

Abstract

PURPOSE:To execute an MVCL instruction at a high speed by converting dynamically the operand address of an instruction in an access register mode with use of an access register of a CPU and an access list stored in a main storage. CONSTITUTION:The base register number is set to a latch 1 in a cycle B, and the corresponding access register is selected under the AND conditions secured between the decoding result of the base register number and a B-mu-TAG signal, i.e., the access register read signal obtained in the cycle B. The contents of the access register are once held by a latch 5 and then sent to an arithmetic unit 6. This operation is applied to the 1st and 2nd operands of the corresponding MVCL instruction, and the data on both operands are compared with each other by the unit 6. The result of this comparison is converged by the OR circuits 8-1 - 8-n and 9 and held by a latch 11 in response to the signal received from an AND gate 10. Meanwhile the data are shifted despite the detection 12 of an INH-DISABLE-OVERLAP-CHK signal.

Description

[Detailed Description of the Invention] [Summary] The MVCL is a virtual memory type information processing device that can operate in co-access register mode, and is designed to speed up the operation speed of MVCL instructions.
For the first and second operands of the instruction word, if there is no register number for specifying the operand address, select the contents of the access register corresponding to the corresponding register number, while specifying the operand address. means for setting the data as all "0" when the register number is 0; and means for comparing the data related to the first operand selected or set by the means with the data related to the second operand. , the comparison result is used to control whether or not to check for destructive overlap between the addresses of the first and second operands.

[Field of Industrial Application] The present invention relates to checking for destructive overlap when moving data in real space in an information processing device having a virtual storage device consisting of a plurality of address spaces, and in particular
The present invention relates to a means for quickly controlling whether or not to check for destructive overlap regarding addresses designated as a first operand and a second operand when an instruction is executed.

[Background Art] Recent demands on information processing devices include an increase in the amount of data to be processed. This is particularly noticeable in database systems. In line with this demand, there is a need to realize an architecture that allows a user program to directly access data in multiple address spaces, exceeding the address space limitations of conventional virtual storage devices.
A product like this has appeared.

That is, in a conventional information processing device having virtual memory, only accessing data within a single address space specified by a control register is permitted. Therefore, in order to refer to data in multiple address spaces, it is necessary to change the contents of the control register, which is under the control of the operating system. Under such control, user programs were not allowed to directly process data across multiple address spaces. However, as the demand for expansion of virtual memory space increases, there is a need for control that allows user programs to access multiple address spaces with different base register numbers beyond the range of the given address space. It came to be.

As a mechanism for this purpose, the following method can be considered. In other words, a segment table is prepared for each of the multiple address spaces used by the user, multiple segment table origins (STOs) are provided as pointers to the tables, and which one is used is determined based on the pace used in the access. Determined by the contents of the access register indexed by the register number. The method for determining this is actually written (
, the access list in α space is indexed, and which S
It is specified whether to use TO. The above-mentioned access using the access register is described in detail on pages 105 to 109 of the September 12, 1988 issue of Nikkei Computer.

The base register number designation portion is located at a limited bit position of the instruction word, and the contents of the register selected according to the contents thereof are input to an adder circuit for generating an effective address.

The state of an information processing device that performs address conversion using such an address register is called an address register mode, and the address register mode is a program state = word (p
sw).

MVCL (M
OVE CHARACTERLONG) command.

This is an RR-format instruction that moves data at an address in real space that corresponds to information given by the second operand of the instruction word to an address in real space that corresponds to information given by the first operand. (MOVE), and is used when it is necessary to move a relatively large amount of data in real space.

Programmers are generally familiar with the data movement method of MVCL instructions, which reads one byte at a time and writes each byte at the desired address, but in reality, Due to the speed-up and the bus width for reading data from the memory at once, the data read/written at each time is not necessarily one byte at a time.

Therefore, when the first operand address and the second operand address are close to each other, a destructive type mismatch of data may occur.

Normally, one access is made between the first operand data and the second operand data.
By keeping the length to the difference between the operand data, destructive type mismatch can be avoided.

On the other hand, in the address register mode described above, access to multiple address spaces is allowed, but in this case address register conversion is performed, so even if the effective address values of the operands in the instruction path match, Addresses in different real spaces are given.

Therefore, even if the effective addresses are different, destructive contention may occur in real space.

Therefore, when executing an instruction, it is necessary to check whether a destructive type mismatch occurs.

[Problems to be Solved by the Invention] In the access register mode in which access register conversion is performed as described above, the first and second operands of the MVCL instruction are access registers corresponding to register numbers specifying respective operand addresses. Since the contents of the access register should exist within the address space pointed to, destructive type matching is performed only when the contents of the access registers corresponding to the first and second operands match.

Furthermore, if the register number specifying the operand address is zero, the specified operand must exist in the primary virtual storage space, so processing is performed with the contents of the access register being compared as being all zeros.

If you try to implement this kind of processing using the conventional processing method, you will need to check the register number in the microprogram that executes the MVCL instruction, select the access register based on the result, compare the selected contents, and perform a check based on the result. Strict control must be performed, such as branch selection, such as whether or not to perform destructive pattern checking.

FIG. 5 is a flow diagram illustrating a microprogram routine for processing a conventional M V CL instruction.

FIG. 6 further shows the control shown by the flow chart above as a time chart of the vibration line.

The operation will be explained below based on FIG. 5 and FIG. 67. (a) 6th vgJ flow (corresponding to step 16 in FIG. 5) Check the register number of the first operand of the MVCL instruction. The above check is the vibration line B
It is done in cycles. In the W cycle, it is determined whether all 0s are present (the determination result is 5TATUS).

In the case of all O's, since the specified operand exists in the primary virtual storage space, processing is performed with the contents of the access register being compared as all zeros (step 24 in the flowchart of FIG. 5).

(b) Flow ○ in Figure 6 is a dummy stage.

(C) Figure 6 flow■ (Figure 5 step 16j,
As a result of the check in stage (2) above, if the register number is not 0, the contents of the access register corresponding to the number are sent to the arithmetic unit (E unit).

(d) Flows (1) to (2) in FIG. 6 perform the same processing as flows (2) to (2) in FIG. 6 described above regarding the second operand.

(e) In FIG. 6 70-0, the contents of the two access registers are compared in the E unit. The comparison corresponds to step 19 in the flowchart of FIG.

Thereafter, data transfer is started (step 20 in the flowchart of FIG. 5).

If the access register numbers match in step 19 of the flowchart of FIG. 5, a destructive overlap check is performed (steps 21 to 23 of the flowchart of FIG. 5).

As can be seen from the above explanation, the conventional method using microprogram control requires a large number of processing steps, resulting in a large number of processing cycles, which resulted in a score of 8, indicating that high-speed processing cannot be expected. .

The present invention overcomes these conventional problems by dynamically converting the operand address of an instruction using an access register provided in the CPU and an access list in main memory when in address register mode. It is an object of the present invention to provide a means for executing MVCL instructions at high speed in a virtual storage type information processing device configured to be able to refer to data in a plurality of address spaces.

[Means for Solving the Problems] According to the present invention, the above objects are achieved by the means described in the claims.

That is, in the present invention, when in access register mode,
A virtual memory system configured so that data in multiple address spaces can be referenced by dynamically converting the operand address of an instruction using an access register provided in the CPU and an access list in main memory. A control method for MVCL instructions in an information processing device, the MVC
For the first and second operands of the L instruction word, if the register number for specifying the operand address is not 0, select the contents of the access register corresponding to the corresponding register number, and,
The register number for specifying the operand address is 0
When the number is 0, a circuit sets the data as all "0", a circuit compares the data related to the first operand selected or set by the circuit, and the data related to the second operand, and the circuit compares the data related to the second operand. When a result that the data match is obtained, a circuit that holds this result and controls whether or not to use the result to check for destructive overlap between the first operand address and the second operand address. This is an M V CL command control system with

[Function] In the present invention, in the access register mode in which access register conversion is performed, the first MVCL instruction
Since the operand and the second operand should exist in the address space pointed to by the contents of the access register corresponding to the register number specifying the respective operand address, the contents of the access register corresponding to the first operand and the second operand are Destructive overlap checking is performed only when the values match.

Furthermore, if the register number specifying the operand address is zero, the specified operand must exist in the primary virtual storage space, so processing is performed with the contents of the access register being compared as being all zeros.

In the conventional processing method, the microprogram that executes the MVCL instruction checks the register number, selects the access register based on the result, compares the selected contents, and checks whether or not to check for destructive overlap based on the result. However, in the present invention, these processes are performed by hardware, so high-speed processing can be expected.

[Embodiment] FIG. 1 is a block diagram showing an embodiment of the present invention,
1 is a latch that holds the pace register number of the B cycle, 2 is a decoder, 3-1 to 3-n are AND gates, 4 is an access register, 5 is a latch, 6 is an arithmetic unit, and 7 is an address address by the arithmetic unit. A latch that holds the comparison result (exclusive OR (EOR) result), 8-
1 to 8-n and 9 each represent an OR gate, 10 an AND gate, 11 a latch, and 12 a destructive overlap condition detection circuit.

FIG. 2 is a time chart showing an example of the operation of the above embodiment.

In Figure 1, the base register number is set in γchi1 in the B cycle, and the decoding result and B-μ-TA, which is the access register read signal in the B cycle, are
The corresponding access register is selected by the AND condition with the G signal, and after its contents are temporarily held in the latch 5, they are sent to the arithmetic unit 6 (E unit of the CPU).

The above operation is performed as shown in the time chart of Fig. 2.
This is performed on the first and second operands of the VCL instruction, and both data are compared by the arithmetic unit 6 (this comparison is actually obtained as an exclusive OR of both data, and the result is used as the comparison result). Become). The comparison results are collected by OR circuits 8-1 to 8-n and 9 and held in latch 11. The circuit consisting of the AND gate IO is a circuit that creates timing for setting data to the latch 11.

The output of the OR gate 9 is 0" (this being "0" means that the exclusive OR of the contents of the access registers corresponding to operands I and 2 is all "0"), While this is held by latch 11, I NH-D I 5A as shown in FIG.
The BLE-OVERLAP-CHK signal is up, and in this situation the Dr 5ABLE-OVERLAP-CH
Even if the K signal is detected, data movement continues as usual.

FIG. 3 is a block diagram showing an example of the configuration of the destructive overlap condition detection circuit 12, in which 13 is a B-latch (
B-LATCH), 14 is C-Latch (C-LATC
H), 15 is CO-Latch (CO-LATCH),
16-1 to 16-3 represent AND gates.

In the same figure, B-LATCH is a latch that holds the result when the condition (OPl address) ≧ (O20 address) is detected (the above OPI holds operand l, and O20 holds operand 2). It represents.

The same expression will be used hereafter).

Further, C-LATCF( is a latch that holds the result when the condition [MIN(○PI length, OP2 length)-1-OP2 address 3>OPI address) is detected.

Furthermore, C0-LATCH is CMIN (OF rungs,
OP2 length>4-OF2 address]>○P2 address This is a latch that holds the result when the condition is detected, and when this latch is set, it indicates that operand 2 will not wrap around.

Each of the above conditions is detected by looking at the carry of a special adder.

The AND condition of AND gate 16-1 in Figure 3 is
B-LATCHHC-LATCH, and the AND condition of AND gate 16-2 is B-LATCHHCO-LA
TCH, and the AND condition of the AND gate 16-3 is C-LATCHHCO-LATCH, and if any one of these is satisfied, it becomes a destructive overlap condition.

FIG. 4 is a diagram illustrating the conditions that cause such destructive overlap (overlap), and (a)
is B-LATCI (reward of data overlap when the HC-LATCH condition is satisfied, (b) is B-LATC)
(The state of data overlap when the HCO-LATCH condition is satisfied, (C) is C-LATCHMCO-LAT
It shows the state of data overlap when the CH condition is satisfied.

In the figure, 0PIA indicates the first address of operand 1, and OP2Δ indicates the first address of operand 2.

[Effects of the Invention] As explained above, according to the present invention, in the access register mode, by dynamically converting the operand address of an instruction using the access register provided in the CPU and the access list in the main memory. In a virtual memory type information processing device configured to be able to refer to data in multiple address spaces, the determination result of whether or not to check for destructive overlap of data upon execution of an MVCL instruction is determined. Since it can be obtained quickly, there is an advantage that the processing speed of MVCL instructions can be increased.

FIG. 5 is a flow chart showing a microprogram routine for conventional MVCL instruction processing, and FIG. 6 is a pipeline time chart showing conventional MVCL instruction processing control.

1.5, 7.11... Latch, 2...
Decoder, 3-1 to 3-n, 16-1 to 16-3.
10-AND gate, 4...Access register, 6...Arithmetic unit, 8-1 to 8-n, 9.
...OR gate, 12...Destructive overlap condition detection circuit, 13...B-latch, 1
4...C-Latch, 15...CO-Latch, 16-24...Operations on the flowchart

[Brief explanation of drawings]

Claims (1)

[Claims] When in access register mode, data in multiple address spaces is referenced by dynamically converting the operand address of an instruction using an access register provided in the CPU and an access list in main memory. MVCL in a virtual memory type information processing device configured to enable
In the instruction control method, when the register number for specifying the operand address for the first and second operands of the MVCL instruction word is not 0, the contents of the access register corresponding to the corresponding register number are selected. , on the other hand, when the register number for specifying the operand address is 0, there is a circuit that sets the data as all "0", data related to the first operand selected or set by the circuit, and data related to the second operand. When the above circuit obtains a result that both data match, it holds this and uses the result to compare the first operand address and the second operand address. 1. An MVCL command control system characterized by comprising a circuit for controlling whether or not to perform a destructive overlap test.