JP2915680B2 - RISC processor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pipelined RISC processor.

[0002]

2. Description of the Related Art Generally, in a processor which is a central processing unit of a computer, when an address for referring to or changing a memory is designated by an instruction, if the address is embedded in the instruction word, the number of bits which can be designated in the address <the instruction word Becomes the number of bits. And in the RISC processor,
The number of bits of the instruction word is fixed, and the number of effective bits of the address is usually equal to or greater than the number of bits of the instruction word, so that all bits of the address cannot be used effectively. .

Therefore, conventionally, in a RISC processor, (1) an arithmetic operation instruction sets a part of an address value in a register, usually an upper bit (bit) which cannot be specified by a value embedded in an instruction word, 2) A processing method is used in which memory access is performed by addressing the sum of the value of the register and the value embedded in the instruction word, and all the effective address bits are used. At this time, since the value set in the above (1) is also embedded in the arithmetic operation instruction, it is not possible to specify all the address bits only by the process of (1).

[0004]

However, such a conventional RISC processor has the following problems. That is, the value embedded in the instruction word is extracted at the stage of instruction decoding, but in the address generation method using two instructions as described above, the value extracted in (1) is not extracted. It is necessary to wait for the memory access of (2) until the processing of the executed arithmetic operation instruction is completed, so that a waiting time is generated in the address generation processing, and there is a problem that the arithmetic processing time becomes slow as a whole.

To explain this point in more detail, the configuration of the portion that performs the address generation processing of the conventional RISC processor is as shown in FIG. 3, and includes a register file 1, an instruction decoder 2, an address generation section 3, An arithmetic operation unit 4 and registers 5 to 7 are provided. The register file 1 is a block for storing data used for the operation and data of the operation result, and the instruction decoder 2 decodes the instruction and sends a numerical value embedded in the instruction to each of the blocks 3 and 4. It is a working block. The mechanism by which the instruction decoder 2 fetches an instruction is omitted.

Further, an address generation unit 3 calculates an address from data from the instruction decoder 2 and the arithmetic operation unit 4,
The arithmetic operation unit 4 is a block that functions to output to the address line 8 and that performs an operation to the register file 1 and its own data.

In such a conventional RISC processor, when performing an address generation process,
The steps shown in FIG. 4 were taken.

<< Step 1 >> Setting (Decoding) Address High-Order Bit to Register Instruction decoder 2 decodes "instruction 1", instructs arithmetic operation unit 4 to execute an arithmetic operation, and sets a value to be set. Is also extracted from the “instruction 1” and sent to the arithmetic operation unit 4.

<< Step 2 >> Setting (Execution) Address High-Order Bit to Register The arithmetic operation unit 4 sets the value sent from the instruction decoder 2 to the high-order bit.

<< Step 3 >> Data Loading (Decoding) The arithmetic operation unit 4 writes the value of the upper bit of the address into the register of the register file 1 and simultaneously sends the same value to the address generation unit 3. Then, the instruction decoder 2 decodes the “instruction 2”, instructs the address generation unit 3 to calculate an address, extracts the value to be added to the value from the arithmetic operation unit 4 from the “instruction 2”, and generates the address. Send to Part 3.
The address generator 3 adds these two values to obtain a regular address.

<< Step 4 >> Data Loading (Execution) The address from the address generator 3 is output to the address line 8 and the data line 9 waits for data.

<< Step 5 >> Data Load (Write) The value of the data line 9 is written to the register file 1.

In this way, address generation and data write processing are performed in five steps.
In << Step 2 >>, an arithmetic operation unit is used to set the upper bits of the address in the register by spending one step, but the processing is not so complicated. In other words, it is a simple process that simply puts a value whose value is already known at a predetermined bit position. However, spending one step for such a process slows down the processing time. is there.

The present invention has been made in view of such a conventional problem, and provides a RISC processor capable of improving the processing speed at the time of accessing a memory without changing a program by adding a simple circuit. The purpose is to do.

[0015]

SUMMARY OF THE INVENTION The present invention provides an RISC processor performing a pipeline operation, an operation unit for generating an address, an arithmetic operation unit for performing a data operation, and a function of extracting a value embedded in an instruction word. An instruction decoder having a function of holding the value to be output to the upper bits of the address in the same bit position among the values extracted by the instruction decoder, and having a function of sending the value to the arithmetic unit for generating addresses. At the timing when the instruction decoder takes out the value of the lower address bit embedded in the instruction word, and adds the value of the lower address bit and the value of the upper address bit held in the address upper bit holding register. And output it as address data.

[0016]

In the RISC processor according to the present invention, considering that it takes time to use an arithmetic circuit for a general arithmetic operation to set the value of the upper bits of the address in the register, the register for holding the upper bits of the address is taken into consideration. And the value of the upper bits of the address extracted by the instruction decoder is held at the same bit position of the register for holding the upper bits of the address. To generate the address, the value of the upper bits of the address of the register and the address extracted by the instruction decoder are generated. By adding the value of the lower bit in the operation unit for address generation, there is no need to wait between the set of the address upper bit data and the set of the address lower bit data, thereby enabling high-speed access to the memory.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 shows a circuit configuration of an embodiment of the present invention. In the circuit of FIG. 1, blocks common to those of the circuit of FIG. 3 shown as a conventional example are denoted by the same reference numerals, but blocks 1 to 9 have exactly the same configuration. The feature of the present invention resides in the register 10 for holding the address high-order bits provided between the instruction decoder 2 and the address generation unit 3 and the arithmetic operation unit 4.

This address upper bit holding register 1
0 is a block that functions to hold the value of the address high-order bits generated when the instruction decoder 2 processes “instruction 1” and send it to the address generation unit 3.

Next, the operation of the RISC processor having the above configuration will be described.

As shown in FIG. 2, the RISC of this embodiment
The processor executes the memory access operation by the following four steps.

<< Step 1 >> Setting (Decoding) Address High-Order Bits in Register 10 The instruction decoder 2 decodes the transmitted "instruction 1" and instructs the arithmetic operation unit 4 to execute an arithmetic operation. Then, the value to be set is taken out of the "instruction 1" and sent to the arithmetic operation unit 4 and the register 10 for holding the address high-order bit to be set.

<< Step 2 >> Setting (Execution) and Loading (Decoding) of Upper Address Bits to Address Generation Unit The arithmetic operation unit 4 sets the value sent from the instruction decoder 2 to the upper bits (this is referred to as “step 2”). The value is not used for the operation, but is a process performed to execute the conventional program without changing it.) The instruction decoder 2 decodes the next “instruction 2”, instructs the address generation unit 3 to calculate an address, and sends the value of the address high-order bit from the address high-order bit holding register 10 to the address generation unit 3 ( At this time, the value has already moved to the upper bits).
Further, the value of the address lower bit to be added to the address upper bit is extracted from “instruction 2” and sent to the address generator 3. Then, the address generation unit 3 adds the value of these upper bits of the address and the value of the lower bits of the address.

<< Step 3 >> Data Loading (Execution) The arithmetic operation unit 4 writes a value to the register file 1. The address generator 3 outputs the address to the address line 8.

<< Step 4 >> Data Load (Write) Data on the data line 9 is written into the register file 1.

As described above, the address is generated and output in four steps, the memory is accessed, the data of the corresponding address is obtained from the memory, and the register file 1 is obtained.
Write to. Then, it can be seen that there is no step between the decode execution step of "instruction 1" and the decode execution step of "instruction 2", as compared with the case of FIG.

In the RISC processor, the efficiency is maximized when there is no space between the execution steps of the instruction. Therefore, in the present embodiment in which the space between the execution steps can be eliminated in this way, the processing speed is reduced. It will be faster.

In the above-described embodiment, "instruction 1" for setting the upper bits of the address is a normal arithmetic instruction, and an arithmetic operation is performed to maintain compatibility when a conventional program is executed. The unit 4 performs the operation as instructed. When the "instruction 1" is decoded, a value is set in the address upper bit holding register 10 regardless of whether or not the next "instruction 2" is a data load. In this case, there is no need for a mechanism for determining what the next “instruction 2” is. In this way, the conventional program can be used without modification in this system.

The present invention is not limited to the above-described embodiment, and can be widely used when the memory access by two instructions is frequently performed by the RISC software without any change.

[0030]

As described above, according to the present invention, an address high-order bit holding register is prepared, and the value of the address high-order bit extracted by the instruction decoder is held at the same bit position in the address high-order bit holding register. In the address generation, the value of the upper bits of the address of this register and the value of the lower bits of the address extracted by the instruction decoder are added in the operation unit for address generation so that the set of the upper bits of the address and the lower bits of the address are added. This eliminates the need to wait between sets of, and enables high-speed access to the memory. Therefore, a processor architecture having a large number of programs having a large number of instructions for accessing the memory can be executed at high speed without rewriting the programs.

[Brief description of the drawings]

FIG. 1 is a functional block diagram of one embodiment of the present invention.

FIG. 2 is an operation explanatory diagram of the embodiment.

FIG. 3 is a functional block diagram of a conventional example.

FIG. 4 is an operation explanatory diagram of a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Register file 2 Instruction decoder 3 Address generation part 4 Arithmetic operation part 5-7 Register 8 Address line 9 Data line 10 Address high-order bit holding register

Continuation of the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G06F 9/30-9/355 G06F 9/40-9/42 390

Claims (1)

(57) [Claims] 1. An RISC processor performing a pipeline operation, comprising: an operation unit for generating an address; an arithmetic operation unit for performing a data operation; an instruction decoder having a function of extracting a value embedded in an instruction word; An address high-order bit holding register having a function of holding the value to be output to the address high-order bit of the value extracted by the decoder at the same bit position and transmitting the value to the address generating operation unit; At the timing when the value of the lower address bit embedded in the word is taken out, the value of the lower address bit is added to the value of the upper address bit held in the register for holding the upper address bit, and output as address data. RISC processor.