JPS601655B2 - Data prefetch method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data prefetch method in an information processing apparatus having a cache memory.

Conventionally, there are many techniques related to prefetching of instructions in advance control, but there are very few techniques related to prefetching of operands. However, in an information processing device having a cache memory, necessary operands are accessed each time during execution of data processing from the cache memory, which is associated with the main memory in blocks, but if the operand does not exist in the cache memory, A block is transferred from the main memory to the cache memory, and processing operations are interrupted during this time.

For this reason, it is desirable for information processing devices with cache memory to store as much necessary data as possible in the cache memory, and one way to achieve this is to store data that will be necessary in the near future in the cache memory. A prefetch means is required for block transfer. The present invention relates to the above prefetch control method, and an object of the present invention is to provide a prefetch method for an information processing device that is particularly effective for instructions that process long operands or multiple operands.

The present invention is characterized in that the operands of the currently executed instruction are prefetched regardless of the state of advance control.

Furthermore, the present invention has a function of eliminating the trouble caused by prefetching. That is, since the processor is not stopped while prefetching is being performed, a new READ request or WR request is made to the same block before the prefetching operation is completed.
ITE requests may occur. Therefore, the RE
If an AD request is generated during a prefetch operation, the same block in the main memory and IJ will be accessed twice, resulting in wasted time. Additionally, if a WRITE request is made during prefetching, the contents of main memory and cache memory will be inconsistent. Therefore, in the present invention, in order to prevent the above-mentioned failure from occurring, when a data transfer request occurs for the same block as the prefetch,
The apparatus includes means for making the processing of the data transfer request wait until the prefetch is completed.

Hereinafter, the data prefetch method of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing a schematic configuration of an information processing device having a cache memory.

At the same time, 1 main memory, 11 is cache memory that holds data associated with main memory 0 in blocks, and cache memory 11 is composed of memory elements that can be accessed faster than main memory 0. Needless to say. 12 is an arithmetic control unit that executes arithmetic operations; 13 is an instruction control unit that executes instruction decoding, instruction branch control, operand address calculation, operand access, etc.; and 14 is an instruction control unit 13 or an arithmetic control unit 12 and a cache. A memory access control section 15 that controls data transfer with the memory 1 or the main memory 0 is a control storage section necessary for the microprogram control method. Although FIG. 1 shows an embodiment of the information processing device controlled by a microprogram, the present invention is based on the control storage unit 15.
The present invention can be implemented satisfactorily even with an information processing device controlled by hardware that does not have a hardware control system. FIG. 2 is an example of an instruction format to which the prefetch method of the present invention is applied.

The instruction word shown in the figure is the instruction code and operand 1.
AI, A2, and A3 in the operands and operands 3 are the respective address parts, and T1, T2, and T3 are the respective data types (code format of 1-bod Hayabusa number, 1-bob Hayabusa code format, ), N1, N2, and N3 indicate the operand length of each decimal number or character. Assume that this instruction is an instruction that operates on the data of operand and operand 2, and stores the result in operand 3. FIG. 3 shows an embodiment in which the depth of advance control to which the prefetch method of the present invention is applied in the information processing apparatus shown in FIG. 1 is set to three stages.

In the figure, the processing operation performed by the instruction control unit 13 is called one cycle, and this one cycle executes decoding of an instruction, calculation of an operand address, generation of a memory command, conversion of a page address into a real address, etc. Furthermore, the processing operations performed in the memory access control unit 14, cache memory 11, and main memory 10 are referred to as a C cycle.
In the cycle, the data transfer request generated in the previous cycle is received, the cache memory 11 or the main memory 0 is accessed as necessary, and the accessed data is transferred to the arithmetic control section 14 if necessary.
Furthermore, the processing operation performed by the arithmetic control unit 14 is referred to as an E cycle, and this E cycle is performed by the memory access control unit 14.
The calculation is performed using the data transferred from. Now, with reference to the timing chart of FIG. 4, the processing operation when the three-stage advance control method shown in FIG. 3 is adopted and the instructions of FIG. 2 are executed will be explained.

In Figure 4, 1, C, and E are 1 cycle in Figure 3, and C
It corresponds to processing in cycle and E cycle. When the advance control of the present invention is applied to the execution of the instruction shown in FIG.
The instruction is sent from the instruction buffer 1 (not shown) to the instruction control unit 3, and the instruction is decoded. At time point 11, the instruction control unit 13 determines that there are multiple instruction words and that the instruction is for prefetching. Next, at step 12, the next word of the instruction (related to the operand) is sent from the cache memory 11 to the instruction control section 13, and the address of operand 1 is calculated by the operand address generation circuit.

The address of operand 1 is converted by the page address conversion circuit, and at the same time, the address is transferred to the memory address control unit 14, and at the same time, the address is transferred to the instruction control unit 13.
A briffet request command is transferred from the memory command generation circuit in the memory access control unit 14. Next 13
Then, the next word of the instruction (related to operand 2) is transferred from the cache memory 11 to the instruction control unit 13, and similarly to the above, the operand address generation circuit generates the operand 2.
address is calculated.

The address of this operand 2 is also converted by the page address conversion circuit, and the address and the prefetch request command from the memory command generation circuit are transferred to the memory access control unit 14. CI of C cycle is processed in parallel at the same timing as this 13.
That is, in the CI, upon receiving the prefetch request generated in step 12, the memory access control unit 14 checks whether a block having the requested address exists in the cache memory 11, and if it does not exist in the cache memory 11, the block is sent to the main memory 10. A block transfer request is generated. The data resulting from this block transfer is written into the corresponding block of the cache memory 11, but is not transferred to the arithmetic control unit 12. On the other hand, if a block having the requested address exists in the cache memory 11, the memory access control unit 14 does not perform any processing in response to the prefetch request.

Next, in step 14, a word regarding operand 3 of the instruction is sent from cache memory 11 to instruction control section 13, and address calculation for operand 3 is performed.

Since the address of operand 3 indicates a store operand, there is no need for prefetching. At C2, which is the same timing as 14, the prefetch request for operand 2 generated in 13 above is processed. The processing of this prefetch request is the same as the prefetch request for operand 1 executed by the CI described above. If there is no block in the cache memory 11 that has the address requested for prefetching of operand 2, the block is read from main memory 0. A block transfer is performed and the data is secured in the cache memory 11. Finally, in EI to EN processed in the E cycle, actual instructions are executed.

That is, operand access, operation execution, and result storage are performed using the addresses calculated in steps 12 to 14 above. In the above embodiment, a prefetch request is generated at the initial stage of one cycle of advance control, and commands indicating prefetch requests for operands 1 and 2 are sent to 12 and 13 in FIG. 4 in the instruction control unit 13. This was generated from the memory command generation circuit to the memory access control unit 14.

However, the prefetch request is not limited to the above embodiment; for example, the control storage unit 15 shown in FIG. 1 may be provided with a function of generating a prefetch request. Note that in an information processing apparatus that does not have the control storage section 15, the arithmetic control section 12 shown in FIG. 1 may be provided with a function of generating a prefetch request. Next, the processing operation when the control storage section 15 described above is provided with a function of generating a prefetch request will be explained with reference to the timing chart of FIG.

Note that the timing chart shown in FIG. 5 shows an example of the execution of control instructions used in an operating system or the like. In the above control command, A, B
, C, which requires preprocessing, operand access, and arithmetic processing for the three operands. Prefetch in this case will be explained below. First, 1
In the cycle, instructions are decoded.

Operand access is performed in the next C cycle, and no prefetch is performed at this time. In the next E cycle, this instruction is mainly executed. That is, preprocessing regarding operand A is performed during the EI period. Next, in period E2, operand A is prefetched at the same time as operand B is preprocessed. Next, during period E3, access and arithmetic processing of operand A are performed. At this stage of E3, since operand A has been prefetched at E2, access and arithmetic processing of operand A may be executed. Next, in period E4, prefetching of operand B is performed simultaneously with preprocessing of operand C.
Next, in period E5, access and arithmetic processing of operand B are performed. At this stage of E5, since operand B has been prefetched at E4, access and arithmetic processing of operand B can be executed. Finally, in period E6, access and arithmetic processing of operand C are performed. As mentioned above, when there is other work that must necessarily be done before operand access, excellent effects can be achieved by actively bringing it to the front stage and performing prefetching at the same time. In order to use the prefetch operation described above more effectively,
It is better to perform the actual operand access after the block transfer by prefetch is completely completed, but if the data transfer of the main memory 10 for prefetch is delayed, or if the operand access after prefetch is delayed by the instruction control unit 13 or If the arithmetic control unit 12 issues the operand at an early stage, there is a possibility that a new operand access will occur before the prefetch is completed.

That is, if a new operand access is made outside the same flop before prefetching is completed, double data transfer requests may be output to the same block of the main memory. When you are in a situation like this,
Not only will the effect of prefetching be lost, but it may also cause a delay in subsequent operand access. Further, when a write request is generated in the same block as the prefetch for some reason, if the write request is accepted before the prefetch is completed, the contents of the main memory 10 and the cache memory 11 will be inconsistent. In this case, it is necessary to write to the cache memory 11 according to the write request after the prefetch has finished writing to the cache memory 11. In the present invention, the cache directory is devised so that when a new data transfer request occurs to the same block in the cache memory before the data transfer caused by the prefetch request command is completed, the same block in the main memory is It has a function to prevent double access.

FIG. 6 shows an embodiment of the above cache directory.

In the figure, AO to AN are virtual addresses, VO to VN are validity bits that indicate whether the contents of the directory are valid, and PO to PN are non-rawand robin counters that can determine which block to use using the algorithm. The pending bit indicates that the data transfer due to the prefetch request has not been completed, and the RR indicates the next block to be used. to show the application. The control of data transfer in the information processing apparatus of FIG. 1 when using the cache directory shown in FIG. 6 will be described below with reference to the flowchart of FIG. 7. In the present invention, when a data transfer request occurs, the pending bit is checked, and if the pending bit is set, a prefetch request was previously output for the same block and the transfer of the block has been completed. means no,
Processing of the data transfer request is awaited until the pending bit is reset, ie, the prefetch operation is completed. That is, in FIG. 7, when a data transfer request is transferred from the instruction control section 13 or the arithmetic control section 12 to the memory access control section 14, the memory access control section 14 checks the pending bit of the corresponding block using SI.

When the pending bit is 1 and the directory is bit, the same block is waiting for data transfer by prefetch, so the data transfer request cannot be accepted until the pending bit becomes 0. When the pending bit becomes 0 and the data transfer request is accepted,
The type of memory command is checked in S2.

For example, if the memory command is a write command, it is checked in S3 whether a corresponding block exists in the cache memory 11. When the corresponding block exists (hit) in the cache memory 11, data is written to the corresponding block in the cache memory 11 in S4, and a write data transfer request is issued to the main memory 0 in S5. However, the corresponding block is cache memory 1
If it does not exist in cache memory 1 (miss hit), cache memory 1
No data is written to the main memory 01, and a write data transfer request is issued to the main memory 01 in S5. The write operation then ends. Next, the type of memory command is S.
When checked in step 2, if it is a read command, it is checked in step S6 whether it is a normal read request or a prefetch request.

In the case of a normal read request, it is checked in S7 whether the corresponding block exists in the cache memory 11, and if it exists (hit), the corresponding block in the cache memory 11 is accessed in S8, and the read data is is transferred to the arithmetic control unit 12 or instruction control unit 13, and the process ends. On the other hand, if the result of checking in S7 is that the corresponding block does not exist in the cache memory 11 (mishit), the execution of the arithmetic control unit 12 and instruction control unit 13 is stopped in S9,
A read request is issued to SI Kawakoteoh Shimori 101. When the transfer of the lj code data from the main memory 10 in the SII is completed, the read data is written in the corresponding block of the cache memory 11 in S12, and then the read data is written in the corresponding block of the cache memory 11 in S12.
sets the validity bit of the corresponding block in the directory. When the corresponding block is secured in the cache memory 11 as described above, the read data is transferred to the arithmetic control unit 12 or the instruction control unit 13 in SI4, and the execution of the arithmetic control unit 12 or instruction control unit 13 is performed in S15. Restart and end.

By the way, when it is determined in S6 that it is a prefetch command, the process proceeds to S16, and the S
At step 16, it is checked whether the corresponding block exists in the cache memory 11. Then, when the corresponding block exists in the cache memory 11 (hit), the process ends without performing any operation in response to the prefetch command. However, if the corresponding block does not exist in the cache memory 11 (mishit), the corresponding pending bit of the directory is set in S17, and a read request is issued to the main memory 1 in S18. This read request is different from the normal read request processing shown in S9 to SI5, in which the execution operations of the arithmetic control section 12 and instruction control section 13 are continued without being stopped. And SI9
When the read data transfer from the main memory 10 is completed in step S20, the read data is transferred to the cache memory 11.
is written to the corresponding block. At this point, the data is not transferred to the arithmetic control section 12 or instruction control section 13. Next, in S21, the pending bit of the corresponding block in the directory is reset, and the valid bit is set, and the operation ends.

As described above, the present invention has the following features and effects. First, in the present invention, the algorithm for generating a prefetch request is generated at a valid time during instruction execution, also for operands that will be required in the near future by the currently executing instruction.

For this reason, this method is unique, unlike the original prefetch that will be performed in an information processing apparatus that employs a future advance control method or the prefetch that is performed using idle time of advance control. Second, it exhibits an excellent prefetch effect for instructions with long operands or multiple operands. That is, decimal instructions, instructions that handle characters, control instructions used in operating systems, etc. often have long operands spanning multiple operands. The present invention allows the timing of issuing a prefetch request to be easily selected during the execution of such an instruction. Third, the length of the operand to be prefetched can be arbitrarily selected. That is, in the present invention, since a prefetch request is issued during the execution of an individual instruction, it is possible to prefetch an operand of a length suitable for that instruction. Fourth, the probability that prefetched data will be used is extremely high.

In the case of a prefetch performed in conventional advance control, if a branch by a branch instruction is unexpected, the previously issued prefetch may become meaningless. However, in the present invention, since a prefetch request is generated for data that will be needed in the near future during the execution of an instruction, the probability that the prefetched data will be used is extremely high.

Fifth, even if a new data transfer request occurs to the same block in the cache memory before the data transfer is completed, which also involves a prefetch request command, double access to the same block in the main memory should be prevented. I can do it.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an information processing device to which the prefetch operation of the present invention is applied, FIG. 2 is a diagram showing an embodiment of a format requiring the prefetch operation of the present invention, and FIG. 4 is a timing diagram illustrating pre-IJ fetch processing in the instruction format shown in FIG. 2, and FIG. 5 is a timing diagram illustrating other prefetch processing. , FIG. 6 is a diagram showing an embodiment of the cache directory 1 applied to the prefetch processing of the present invention, and FIG. 7 is a flowchart showing the operating procedure of the information processing apparatus of FIG. 1 having the cache directory 1 of FIG. 6. It is. 10...Main memory, 11...Cache memory, 12...
...Arithmetic control section, 13...Instruction control section, 1
4. ．．・．． ...Memory access control unit. O figure O Z figure Gummy Zuko 4 figure next 5 figure next 6 figure next 7 figure

Claims (1)

[Claims] 1. A main memory, a cache memory that stores data associated with this main memory in blocks, an instruction that processes long operands or operands that exist in multiple locations, and a If the data of the operand to be executed does not exist in the cache memory, a prefetch means stores the data of the operand from the main memory to the cache memory by block transfer; The data prefetch is characterized by comprising means for causing processing of the data transfer request to wait until block transfer to the cache memory by the prefetch means is completed when a new data transfer request is generated. method.