JPS61133440A - Data processing unit - Google Patents

Abstract

PURPOSE:To prevent delay in start of address calculation due to wait for confirmation of a corresponding register by using an output of an effective address stack in place of an output of an index register so as to execute the address calculation. CONSTITUTION:When an effective address setting instruction is set to an instruction register 10, the effective address read from an effective address stack 15 is selected by a switch 35 and set to the 1st working register 37. The content of the said register is written in a work memory 32 and an index register 12. When it is detected that a succeeding instruction is address modification designation using the index register 12, a switch 18 is read from the effective address stack 15 and the effective address of the preceding effective address setting instruction is selected as a value after the execution of the said instruction in place of the output of the index address register 12. Then the preceding effective address setting instruction executes address calculation without awaiting the end of data write to the index register 12.

Description

DETAILED DESCRIPTION OF THE INVENTION (Applications for Child Work e) The present invention relates to a data processing device, and particularly to a method for improving a reduction in processing speed due to contention of general-purpose registers during address calculation.

(Prior art) ′ Generally, in an instruction used in a digital computer, the address of the operand used in the instruction is determined by the contents of one of the general-purpose registers including the index register specified by the instruction, and the internal displacement address of the instruction. This operation is called index modification. Of course, the contents of the general-purpose register reflect all the calculation results of the instruction preceding the instruction that performs the address calculation.

In particular, in the pipeline processing 1i method in which the address of the next instruction is calculated before the execution of the previous instruction is completed, the update status of general-purpose registers by the preceding instruction in the data processing device is registered and managed. When a subsequent instruction appears that performs address calculation using a general-purpose register that has not yet been executed, it is necessary to delay the address calculation until writing to the corresponding general-purpose register is completed.

Such general-purpose register contention has been a factor in reducing instruction processing speed.

On the other hand, when processing array data, a coding method that combines general-purpose register update instructions and index modification has been widely adopted. For example, as shown in FIG. 2, FORTRAN is developed into machine language. The machine language instruction FliAXO, 1, XO is an instruction to set the generated effective address (1+X0) to the fc index register XO, and the effective address (1+XO) can be determined at the time of address calculation. This value is the immediately following multiplication instruction MULTo.
, is used in the index modification of Xo. Therefore,
The conventional method is EAX.

Address calculation for the MULTo and Xo instructions had to wait until the execution of the instructions was completed.

(Problems to be Solved by the Invention) Therefore, as explained above, there is a drawback that the instruction processing speed is reduced due to contention of general-purpose registers used for address calculation.

An object of the present invention is to eliminate the above-mentioned drawbacks by using the output of the effective address stack instead of the output of the index register for address calculation, and to set the preceding effective address to a general-purpose register and the subsequent instruction. An object of the present invention is to provide a data processing device configured so as to be able to improve the delay in address calculation caused by contention during read 1c for address generation.

Means for Solving Problem C) A data processing device according to the present invention includes a storage device, an instruction control device, and an instruction execution device, and the instruction control device includes an effective address adder, an effective address stack, Comprising an index register and reading means,
It is contemplated that the effective address read by the reading means is used as the contents of the index register in address calculation of a subsequent instruction.

The effective address adder is for adding effective addresses, the effective address stack is for holding the result of the addition, and the index register is for storing effective addresses.

The reading means is for reading the contents of the effective address stack as an effective address when the same contents are successively read from the index register.

(Example) Next, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a data processing apparatus according to the present invention. In FIG. 1, 1 is an instruction control device, 2 is a storage device, 3 is an instruction execution device, 10 is an instruction register, 11 is a base register, 12 is an index register, 13 is a virtual address adder, and 14 is an effective address adder. , 1g is an effective address stack, 16 is a decoder, 17 is an operation instruction stack, 18, 35, 36 are respective switches, 21 is a virtual address register, 22 is an address translation buffer, 23 is an address array, 24 is a data array, 31 is a data buffer, 32 is a working memory,
33 is an arithmetic unit, 37 and 38 are working registers,
39 is a control circuit.

In FIG. 1, parts not directly related to the present invention are omitted.

In FIG. 1, the instruction control unit f1 reads the instruction from the storage device 2, decodes it, creates control information including branch conditions and update target register designation code, and decodes the address designation code in the instruction. 6t creates an effective address and sends both to instruction execution unit f3. As a result of the decoding, if the instruction requests reading or writing from the storage device 2, a virtual address is calculated and sent to the storage device 2. The storage device 2 writes or reads the requested data to the data array 24 of the buffer memory or to the main memory. The instruction execution device 3 performs calculations using the contents of each register instructed by the instruction control device 1, and updates the contents of various registers or storage devices.

In the instruction control device 1, the instruction word set in the instruction register IO consists of four fields: Op+ br X + and y. The op field contains an instruction code, which is decoded by the decoder 16, part of which is used to control each block inside the instruction control device l, the other part is used as a request signal to the storage device 2, and the other part is used as a request signal to the storage device 2. is used as operation instruction information to the instruction execution device 3 and is stored in the operation instruction stack 17.

The b field of instruction register 10 is used as a register designation number and sent to pace register 11. The X field of instruction register 10 is used as a register designation number and sent to index register 12. The base address read from the pace register 11 and the index read from the index register 12 are added to the X field (displacement address) of the instruction register IO by the virtual address adder 13 and used to generate a virtual address. Ru. Effective address adder 14
In , the same index and the X field are added to form the effective address. The output of the effective address is stored in the effective address stack 15.

The output of one of the series is supplied to the instruction execution unit #3, and the output of the other series is supplied to the switch 18 for use in place of the above-mentioned index value. The effective address stack 15, O, and operation instruction stack 17 include a plurality of entries, and a decoded instruction before execution can be made to wait until the number of entries.

In the storage circuit 2, a virtual address register 21 holds the virtual address sent from the virtual address adder 13. The address translation buffer 22 is referenced by the output of the virtual address register 21, and the corresponding real address is read from the address translation buffer 22. The address array 23 is referenced by the output of the address translation buffer 22 and the lower address of the virtual address register 21,
It is checked whether the requested operand is registered in the data array 24. If the requested operand is registered, the operand is read from the data array 24 and is sent to the instruction execution device 3 as an operand.
sent to.

In the instruction execution unit R3, the operand sent from the storage device 2 is stored in the data buffer 31. Data buffer 31 has the same number of entries as effective address 15 and operation instruction stack 17, each entry being used for a decoded instruction. The working memory 32 includes a pace register and an index register, and the contents of these registers are updated simultaneously with the pace register 11 or the index register 12. The first operand selected by switch 35 from the output of data buffer 31 , working memory 32 , or effective address stack 15 is set in first working register 37 . Similarly, the second
is set in the second working register 38. The pair of operands set in the first and second working registers 37 and 38 are used for calculation in the calculation unit 33. The obtained calculation results are stored in working memory 3.
2. Pace register 11. and is supplied to the index register 12 and set at the required location.

The above operations are controlled by a control circuit 39 activated by the output from the operation instruction stack 17.

Next, the operation of the effective address setting command will be explained.

When the effective address setting command is set in the instruction register 10, the effective address adder 14 sets the effective address setting command to the instruction register 1.
The X field of 0 and the contents of the index register 12 sent via the switch 18 are added to obtain an effective address and set in the effective address stack 15. At this time, no operand request is sent to the storage device 2. When the instruction execution device i13 executes the above effective address setting instruction, the effective address read from the effective address stack 1!5 is transferred to the switch 3.
5 and set in the first working register 37. The contents of this register are written to the working memory 32 and the index register 12 via the arithmetic unit 33 which is set to through mode according to instructions from the control circuit 39.

When it is detected that the subsequent instruction is an address modification specification using index register lzwo, switch 1
8 is read from the effective address stack 15 and selects the effective address of the preceding effective address setting instruction as a substitute for the output of the index register 12 as the value after execution of the above instruction. Therefore, the address calculation is executed without waiting for the preceding effective address setting instruction to complete writing data to the index register 12.

(Effects of the Invention) As explained above, the present invention executes address calculation using the output of the effective address stack instead of the output of the index register, thereby preventing the start of address calculation while waiting for the determination of the corresponding register. This has the effect of improving delays.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a data processing apparatus according to the present invention. Figure 82 shows the FOR in address calculation based on the conventional technology.
FIG. 2 is an explanatory diagram showing an example of correspondence between TRAN and machine language. l...Instruction control device 2...Storage device 3...
Instruction execution device t1o...instruction register 11.
...Base register 12...Index register 13...Virtual address adder 14...Effective address adder 15...Effective address stack 16...7'=y-ta 17...Operation instruction stack 1
8.35.36...Switcher 21...Virtual address register 22...Address translation buffer 7 23...Address array 24...Data array 31...f-fiA buffer 32...Work Memory 33...Arithmetic unit 37.38...Work register 39...Control circuit

Claims (1)

[Claims] A data processing device comprising a storage device, an instruction control device, and an instruction execution device, the instruction control device including an effective address adder for adding effective addresses, and an effective address stack for holding the result of the addition. and an index register for storing the effective address, and reading means for reading the contents of the effective address stack as an effective address when the same contents are successively read from the index register, A data processing device characterized in that the effective address read by the reading means is used as the content of the index register in address calculation of a subsequent instruction.