JPS5914050A - Memory controlling system - Google Patents

Memory controlling system

Info

Publication number
JPS5914050A
JPS5914050A JP57122661A JP12266182A JPS5914050A JP S5914050 A JPS5914050 A JP S5914050A JP 57122661 A JP57122661 A JP 57122661A JP 12266182 A JP12266182 A JP 12266182A JP S5914050 A JPS5914050 A JP S5914050A
Authority
JP
Japan
Prior art keywords
address
sent
register
memory
multiplexer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57122661A
Other languages
Japanese (ja)
Inventor
Mitsuo Morohashi
Isao Aizawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP57122661A priority Critical patent/JPS5914050A/en
Publication of JPS5914050A publication Critical patent/JPS5914050A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3867Concurrent instruction execution, e.g. pipeline, look ahead using instruction pipelines
    • G06F9/3869Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking

Abstract

PURPOSE:To control reading and writing operations to execute them at the same timing, by constituting a general register of a data processor of two memories. CONSTITUTION:At the timing 1, the data processing circuit sends an address to be read out from a memory 1 as the operand 1 of an instruction A to an address register 3 through a multiplexer 9 under control of a control part 17. The address sent to the register 3 is sent to multiplexers 12, 15, 16 under control of a control part 13 and simultaneously sent and stored to/in an address save register 6. The address sent to the multiplexers 15, 16 is sent to the memory 1 through the multiplexer 15. Receiving the specification of the address, the memory 1 reads out the operand 1 of the instruction A, which is sent to an operation processing part 19 through a multiplexer 18.
JP57122661A 1982-07-14 1982-07-14 Memory controlling system Pending JPS5914050A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57122661A JPS5914050A (en) 1982-07-14 1982-07-14 Memory controlling system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57122661A JPS5914050A (en) 1982-07-14 1982-07-14 Memory controlling system

Publications (1)

Publication Number Publication Date
JPS5914050A true JPS5914050A (en) 1984-01-24

Family

ID=14841500

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57122661A Pending JPS5914050A (en) 1982-07-14 1982-07-14 Memory controlling system

Country Status (1)

Country Link
JP (1) JPS5914050A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61267134A (en) * 1985-05-22 1986-11-26 Hitachi Ltd Data processor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61267134A (en) * 1985-05-22 1986-11-26 Hitachi Ltd Data processor

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