JPS5914050A - Memory controlling system - Google Patents

Abstract

PURPOSE:To control reading and writing operations to execute them at the same timing, by constituting a general register of a data processor of two memories. CONSTITUTION:At the timing 1, the data processing circuit sends an address to be read out from a memory 1 as the operand 1 of an instruction A to an address register 3 through a multiplexer 9 under control of a control part 17. The address sent to the register 3 is sent to multiplexers 12, 15, 16 under control of a control part 13 and simultaneously sent and stored to/in an address save register 6. The address sent to the multiplexers 15, 16 is sent to the memory 1 through the multiplexer 15. Receiving the specification of the address, the memory 1 reads out the operand 1 of the instruction A, which is sent to an operation processing part 19 through a multiplexer 18.

Description

DETAILED DESCRIPTION OF THE INVENTION TECHNICAL FIELD OF THE INVENTION The present invention relates to a memory control system for a data processing device in which a general-purpose register is configured with two memories and data pipeline processing is performed smoothly.

b. Background of the Technology As a method for configuring a general-purpose register of a data processing device having a general-purpose register and an arithmetic processing unit, there is a register system using a memory element. FIG. 1 shows a data processing device in which a general-purpose register is composed of one memory, and a memory and a sioberand 1. The pipeline/processing process of the arithmetic processing unit is shown when there are consecutive instructions to read operand 2, perform arithmetic processing on operand 1 and operand 2, and write the result of the operation to the address of the general-purpose register where operand 1 was located. At timings 1 and 2 in FIG. 1, operands 1 and 2 of instruction AK are read from the general-purpose register, and at timing 3, operation processing of operand 1 and operand 2 of instruction A is performed, and operand 1 of instruction B is read from the general-purpose register. At timing 4, the operation result of instruction A is written into the address of the general-purpose register where operand 1 was located, and the same operation occurs at timing 5 and thereafter.

C0 Prior Art and Problems In a data processing device that has 7 general-purpose registers configured in one memory as described above, arithmetic processing and read operations are performed at the same timing, as shown in timings 3 and 6 in Figure 1. It is possible to overlap the calculation process and the write operation.

However, if you try to execute instructions B and C at a series of timings, at timings 4 and 7, the write operations of instructions A and H that are being executed earlier overlap with the read operations of instructions B and C, respectively. Take shelter.

At this time, one must wait for the operation of one of them.

For this reason, the time required for arithmetic processing increases.

d8 Purpose of the Invention Accordingly, in the present invention, a general-purpose register of a data processing device is constituted by two memories, and is controlled so as to perform reading.

e9 Structure of the Invention The present invention comprises a general-purpose register composed of two memories,
In a data processing device having an arithmetic processing unit, operand 1 and operand 2 are read from memory, and operand 1 is
and operand 2, specifying the address where operand 1 was located, and writing the result of the arithmetic processing to the memory. Even if a read operation and a write operation overlap at one timing, two or more instructions will be executed. By using two memories, read and write operations are attempted to be performed simultaneously.

f3 Embodiment of the Invention FIG. 2 shows a data processing device used in a memory control method which is an embodiment of the present invention, and FIG. 3 shows a data processing device using the data processing device of FIG. A series of data processing unit 3-instructions that reads out 2, performs arithmetic processing on operand 1 and operand 2, and writes the operation result operand 1 to memory.

In Figure 2, 1 and 2 are memories, 3.4.5 is an address register, 6.7.8 is an address save register, and 9
．． 10. 11', 12. 13. 14. 1
5,16° 18 is a multiplexer, 17 is a control unit, 19
represents an arithmetic processing unit.

Now, a continuous data processing instruction A as shown in FIG.

When B, C, etc. are processed by the data processing circuit shown in Fig. 2, at timing 1 in Fig. WJ3, the instruction A
Reads operand 1 of from memory 1.

Furthermore, the same data is written to the same address in memory 1 and memory 2.

At timing 1, the data processing circuit shown in FIG. 2 sends the address to be read from the memory 1 as operand 1 of the instruction A to the address register 3 via the multiplexer 9 under the control of the control section 17.

The address sent to address register 3 is further sent to multiplexer 15.16 via multiplexer 124-, under the control of control unit 13, and simultaneously sent to address save register 6 and stored. The address sent to the multiplexers 15 and 16 is sent to the memory 1 via the multiplexer 15 under the control of the control unit 13.
sent to. Memory 1 receives the address specification and command A
The operand 1 of the instruction A is read out, and the operand 1 of the instruction A is sent to the arithmetic processing unit 9 via the multiplexer 18.

At timing 2 in FIG. 3, operand 2 of instruction A is read out from memory 2. At timing 2, the data processing circuit of FIG. 2 sends the address to be read from the memory 2 as the operand 2 of the instruction A to the address register 3 via the multiplexer 9 under the control of the control section 17. The address sent to the address register 3 is further sent to multiplexers 15 and 16 via the multiplexer 12 under the control of the control section 17. Here, the address of operand 2 of instruction A is not sent to address save register 6. The address sent to the multiplexers 15 and 16 is sent to the memory 2 via the multiplexer 16 under the control of the control section 13.

The memory 2 having received the address reads out the operand 2 of the instruction A, and the operand 2 to the instruction is sent to the arithmetic processing unit 19 via the multiplexer 18.

At timing 3 in FIG. 3, arithmetic processing is performed on operand 1 and operand 2 of instruction A, and operand 1 of instruction B is read from memory 1. At timing 3, the data processing circuit of FIG.
Performs arithmetic processing on operand 1 and operand 2. At the same time, the address to be read from the memory 1 as operand 1 of the instruction B is sent to the address register 4 via the multiplexer 10 under the control of the control section 17.

The address sent to the address register 4 is further sent to the multiplexers 15 and 16 via the multiplexer 13 under the control of the control section 17, and is simultaneously sent to the address save register 7 and stored therein.

The address sent to multiplexer 15.1'6 is sent to memory 1 via. The memory 1 that has received the address reads out the operand 1 of the instruction B, and the operand 1 of the instruction B is sent to the arithmetic processing unit 19 via the multiplexer 18.
sent to.

At timing 4 in FIG. 3, the operation result of instruction A is written to memory 1 by specifying the address address where operand 1 was located, and the operation result of instruction B is written to memory 2 of operand 2.
Reads the data. At timing 4, under the control of the control circuit 17, the data processing circuit of FIG.
to multiplexer 15.16.

The address sent to the multiplexers 15 and 16 is sent to the memory 1 via the multiplexer 15 under the control of the control section 17. And the operation result of instruction A is operand 1
will be written to the address where it was. At the same time, the address to be read from the memory 2 as the operand 2 of the instruction B is sent to the address register 4 via the multiplexer 10 under the control of the control section 17. The address sent to address register 4 is
Further, under the control of the control section 17, the signal is sent to the multiplexers 15 and 16 via the multiplexer 13.

Here, the address of operand 2 of instruction B is not sent to address save register 7. multiplexer 15
．． The address sent to 16 is sent to memory 2 via multiplexer 16 under the control of control circuit 17.

The memory 2 having received the address reads out the operand 2 of the instruction B, and the operand 2 of the instruction B is sent to the arithmetic processor 1 section 19 via the multiplexer 18.

At timing 5 in FIG. 3, the operation result of instruction A is written to memory 2 by specifying the address where operand 1 was located, the operation processing of operand 1 and operand 2 of instruction B, and the operation of operand 1 of instruction C are performed. Read data from memory 1. At timing 5, under the control of the control circuit 17, the data processing device shown in FIG. Sent to multiplexer 15.16. Multiplexer 15.
The address sent to 16 is sent to memory 2 via multiplexer 16 under the control of control section 17. The operation result of instruction A is then written to the address where operand 1 was located.

At the same time, the arithmetic processing unit 19 performs arithmetic processing on operands 1 and 2 of instruction B. At the same time, as operand 1 of instruction C, the address to be read out, such as Memo 1, is sent to the address register 5 via the multiplexer 11 under the control of the control section 17.

The address sent to the address register 5 is further sent to the multiplexer 15, 16 via the multiplexer 14 under the control of the control section 17, and at the same time is sent to the address save register 8 and stored therein. After timing 6, the same procedure as described above is repeated.

y6 Effect of invention★8111 old/r )-, L+lJt r-=+l
The proboscis-'crop, pine, and input operations can be performed, and the time required for pipeline arithmetic processing is reduced.

[Brief explanation of drawings]

Figure 1 shows a data processing device that has a general-purpose register made up of one memory and an arithmetic processing unit, which reads out operands 1 and 2 from the memory, processes operands 1 and 2, and sends the result of the operation to operand 1. This figure shows the pipeline processing process of the arithmetic processing unit when there are consecutive instructions to write to the address of the memory where the previous memory address existed. FIG. 2 shows an embodiment of the present invention. FIG. 3 shows a data processing device used in the memory control method, and FIG. 3 shows the data processing device shown in FIG. This figure shows the pipeline processing process of the arithmetic processing unit when a series of data processing instructions for writing result operand 1 into memory are executed in succession. In FIG. 2, 1 and 2 are memories, 3 and 4.5 are address registers, bt7 and 8 are address savers, multiplexers, 17 is a control section, and 19 is an arithmetic processing section.

Claims (1)

[Claims] In a data processing device that continuously pipeline processes a plurality of data processing instructions including one operation at one timing and composed of a series of a plurality of timings, a general-purpose register is configured with two memories, and the instruction is processed by at least It consists of five timings: a read operation of the first operand, a read operation of the second operand, an arithmetic processing operation, a write operation of the arithmetic processing result data, and a write operation of the arithmetic processing result data, and the arithmetic processing result data is stored in the two memories. A plurality of instructions are written sequentially, a plurality of instructions are piped in with a timing shift of at least two, and a write inactivation of one instruction and a read operation of the next instruction are simultaneously performed on different memories. A memory control method that uses