JPH0512003A - Program control system - Google Patents

Abstract

PURPOSE:To incorporate a large-sized microprogram in an LSI. CONSTITUTION:Plural auxiliary control storages 31, 32, and 33 where the microprogram is stored, plural auxiliary micro instruction registers 41, 42, and 43 where micro instructions read out from auxiliary control storages are stored, decoders 51, 52, and 53 which convert a part of micro instructions stored in auxiliary micro instruction registers to control signals for execution of micro instructions, a main control 10 where start addresses of auxiliary control storages are stored, and a main micro instruction register 20 where start addresses of auxiliary control storages read from a main control storage are stored are provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a micro program control system for an information processing device.

[0002]

2. Description of the Related Art In a conventional micro program control system, a micro instruction read from a control memory is stored in a micro instruction register, and a part of the micro instruction is decoded by a decoder to be a control signal for executing the micro instruction. At the same time, a part of the microinstruction stored in the microinstruction register is used to specify the address on the control memory and store the next microinstruction in the microinstruction register. By this series of operations, an execution sequence of microinstructions is formed, and microprogram control of the information processing device is performed.

In recent years, a large-scale information processing apparatus uses a horizontal microprogram method for executing a plurality of microinstructions in one step in order to increase the speed. The bit width tends to increase. In addition, the number of steps in the microprogram tends to increase because the microprogram performs various controls such as exception processing as well as execution of operations.

[0004]

In the conventional micro program control system, the control memory for storing the micro program becomes large because the capacity of the micro program is increased for speeding up or performing various controls. Therefore, it becomes difficult to embed the control memory in the LSI, which hinders downsizing of the device.

[0005]

A microprogram control system according to the present invention comprises a plurality of sub-control memories for storing microprograms, and a plurality of sub-microinstruction registers for storing microinstructions read from the respective subcontrol memories. ,
From the main control memory, a decoder for converting a part of the microinstruction stored in each sub-microinstruction register into a control signal for executing the microinstruction, a main control memory for storing an activation address of each subcontrol memory, and a main control memory A main microinstruction register for storing the read activation address of each sub-control memory, and a microinstruction is read from each sub-control memory by the activation address of each sub-control memory stored in the main microinstruction register. It is characterized in that a part of the micro-instruction is configured as the next execution address of each sub-control memory. Implementation

FIG. 1 is a block diagram of an embodiment of the present invention.

Referring to FIG. 1, in this embodiment, a main control memory 10, a main micro instruction register 20, three sub control memories 31 to 33, and three sub micro instruction registers 41 to 4 are used.
It is composed of three records 51 to 53.

The main control memory 10 is composed of the sub control memories 31 and 3 respectively.
It is composed of only the areas corresponding to 2, 33 and stores the addresses of the respective sub-control memories 31, 32, 33.

Signal 100 turns on only at the beginning of a software instruction or a particular microprogram processing routine. At this time, the starting addresses of the sub-control memories 31, 32, 33 stored in the main control memory 10 are read out to the main microinstruction register 20, and the sub-control memories 3 are read.
1, 32, 33 are activated.

The micro instruction read from each sub control memory 31 is stored in the sub micro instruction register 41. A part of the micro instruction stored in the sub micro instruction register 41 is decoded by the decoder 51 and becomes a control signal 501 for executing the micro instruction. On the other hand, a part of the micro instruction stored in the sub micro instruction register 41 becomes the next execution address signal 401, and the sub control memory 31
The address above is specified and the next microinstruction is stored in the submicroinstruction register 41. The operations of the sub-control memory 32 and the sub-control memory 33 are similar to the above-mentioned operations of the sub-control memory 31.

As described above, since the capacity of each sub-control memory is reduced by dividing and storing the micro-program composed of micro-instructions into a plurality of sub-control memories, each micro-program should be incorporated in each LSI. Is possible. Further, the main control memory stores only the address of each sub-control memory and has a role of activating each sub-control memory, so that the control memory as a whole can be degenerated and the capacity becomes small.

[0011]

According to the present invention, a microprogram composed of microinstructions is divided and stored in a plurality of sub-control memories, and the main control memory stores only the address of each sub-control memory and activates each sub-control memory. By configuring the role to perform, there is an effect that the capacity of the entire control memory is reduced.

[Brief description of drawings]

FIG. 1 shows an embodiment of the present invention.

[Explanation of symbols]

 10 main control memory 20 main micro instruction register 31 to 33 sub control memory 41 to 43 sub micro instruction register 51 to 53 decoder

Claims (1)

Claim: What is claimed is: 1. A plurality of sub-control memories for storing microprograms, a plurality of sub-microinstruction registers for respectively storing microinstructions read from the respective subcontrol memories, and each of the sub-microinstruction registers. A decoder for converting a part of the stored microinstruction into a control signal for executing the microinstruction, a main control memory for storing an activation address of each subcontrol memory, and each subcontrol memory read from the main control memory And a main microinstruction register for storing the start address of the submicrocontrol register. The microinstruction is read from each subcontrol memory according to the start address of each subcontrol memory stored in the main microinstruction register. A microprogram control method characterized in that it is configured so as to be the next execution address of each sub-control memory.