JPH05298086A - Information processor - Google Patents

Abstract

PURPOSE:To reduce the gate quantity of a control storage capable of changing a microprogram. CONSTITUTION:A main control storage 1 consists of a ROM, and a main microprogram consisting of micro instructions is stored there. An auxiliary control storage 2 consists of a RAM, and an auxiliary microprogram consisting of micro instructions and addresses of the main control storage 1 is stored there. The address of the main control storage 1 read out from the auxiliary control stosrage 2 is compared with the address held in an address register 3 by an address coincidence detecting circuit 5, and a selector 4 selects the micro instruction in the main control storage 1 in the case of noncoincidence but selects that in the auxiliary control storage 2 in the case of coincidence.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control memory of an information processing device using a microprogram.

[0002]

2. Description of the Related Art In recent years, large-scale information processing apparatuses use a horizontal microprogram system which executes a plurality of microinstructions in one step for speeding up. The bit width per hit tends to increase.

In addition, the number of steps in the microprogram tends to increase because not only the execution of operations but also various controls such as exception processing are performed by the microprogram. Since the capacity of the microprogram is increased in this way, the control memory for storing the microprogram is also increased in size.

The conventional main control memory is ROM (read-on memory) or RAM (random access memory).
Composed of. If the control memory is composed of a ROM, the amount of gates will be small, and if it is composed of a RAM, the microprogram can be easily modified.

[0005]

The conventional ROM described above.
In the control memory constituted by, the microprogram is fixed, and there is a problem that dynamic microprogramming or the like becomes impossible. In addition, since the control memory configured by the RAM has a large gate amount, it is difficult to embed the control memory in the LSI, which hinders downsizing of the device.

[0006]

An apparatus of the present invention comprises a main control memory composed of a ROM for storing a main microprogram composed of microinstructions, a microinstruction and an address of the main control memory. And a sub-control memory that is read at the same time as the main control memory and that has an address associated with one of the addresses of the main control memory. Address match detection means for comparing an address with the address of the main control memory read from the sub control memory, and as a result of this comparison, if no match is detected, the micro instruction read from the main control memory And selecting means for selecting the microinstruction read from the sub-control memory when a match is detected. To.

[0007]

Embodiments of the present invention will now be described with reference to the drawings.

Referring to FIG. 1 which is a block diagram of a first embodiment of the present invention, in the present embodiment, a main control memory 1, a sub control memory 2, an address register 3, a selector 4 and an address coincidence detecting circuit 5 are provided. Become.

The main control memory 1 is composed of a ROM.
The microinstruction that constitutes the main microprogram stored in the main control memory 1 is read according to the address stored in the address register 3 and is executed by the selector 4.

The sub-control memory 2 is composed of RAM.
The sub control memory 2 stores a sub micro program composed of micro instructions and the address of the main control memory 1. The access to the sub control memory 2 is performed by using a part of the addresses stored in the address register 3, and all the addresses of the main control memory 1 are associated with any of the addresses of the sub control memory 2. There is.

The reading of the sub control memory 2 is performed at the same time as the reading of the main control memory 1. The address of the main control memory 1 read from the sub control memory 2 is compared with the address stored in the address register 3 by the address coincidence detection circuit 5,
The result of this comparison becomes the select signal of the selector 4. The microinstruction read from the sub control memory 2 is input to the selector 4.

When the address match detection circuit 5 detects a match, the selector 4 selects the micro instruction of the sub control memory 2 and when the match is not detected, selects the micro of the main control memory 1.

Therefore, when the main microprogram stored in the main control memory 1 is changed, the address of the main control memory 1 at the step of changing and the microinstruction after the change may be stored in the subcontrol memory 2. .. By combining the large-capacity ROM and the small-capacity RAM as in the present embodiment, it is possible to change the microprogram and reduce the gate amount.

Referring to FIG. 2 which is a block diagram of the second embodiment of the present invention, in this embodiment, instead of the address coincidence detection circuit 5 in the first embodiment, a valid flag storage circuit 6 is used.
Is provided. The sub control memory 20 stores a sub micro program composed of micro instructions.

A valid flag storage circuit 6 stores a valid flag indicating whether each step of the main control memory 1 is valid or invalid. In this embodiment, it is realized by a RAM of 1 bit × the number of steps of the main control memory. ing.

The access to the valid flag storage circuit 6 is performed at the same address at the same time as the access to the main control storage 1, and the read valid flag becomes the select signal of the selector 4. The selector 4 selects the microinstruction in the main control memory 1 when the valid flag indicates valid, and selects the microinstruction in the sub control memory 2 when the valid flag indicates invalid.

Therefore, when the main microprogram stored in the main control memory 1 is to be changed, the valid flag of the step to be changed is set to invalid and the changed microinstruction is stored in the subcontrol memory 2. .. In this way, it is possible to reduce the gate amount while making it possible to change the microprogram.

In particular, in this embodiment, since it is not necessary to store the address of the main control memory 1 in the sub control memory 2, the bit width of the sub control memory 2 can be reduced, and the sub control memory 2 can be made smaller.
When the number of steps is relatively large, the effect of reducing the gate amount becomes large.

Referring to FIG. 3 which is a block diagram of a third embodiment of the present invention, in the present embodiment, a main control memory 1, a sub control memory 2, an address register 3, a selector 4, a valid flag memory circuit 6, It consists of a decoder 7.

The main control memory 10 stores a horizontal micro program for executing four micro instructions in one step.

Further, the sub-control memory 21 stores one microinstruction and its field information. Here, the field information is information indicating to which of the four micro-instructions that operate simultaneously in one step.

The microinstruction read from the sub control memory 21 is input to all four selectors 41 to 44 for each field. The field information read from the sub control memory 21 is decoded by the decoder 7 and becomes the selector signals of the selectors 41 to 44.

The valid flag read from the valid flag storage circuit 6 is input as an enable signal for the decoder 7. If the valid flag indicates invalid, the selector 41
One of the selectors ~ 44 selects the micro instruction read from the sub-control memory 21, and the remaining three selectors select the micro instruction read from the main control memory 10.

That is, 1 read from the main control memory 10
Of the four micro-instructions of the step, only one micro-instruction is replaced with the micro-instruction read from the sub-control memory 21 according to the field information read from the sub-control memory 21. When the valid flag read from the valid flag storage circuit 6 indicates valid, all the selectors select the micro instruction read from the main control storage 10.
Therefore, when the main microprogram stored in the main control memory 10 is changed, the valid flag of the step to be changed is set to invalid, and the changed microinstruction and its field information are stored in the subcontrol memory 21. Good. While making it possible to change the microprogram in this way,
The gate amount can be reduced.

In particular, in the present embodiment, since it is not necessary to store all the micro-instructions of one step in the sub control memory 21, the bit width of the sub control memory 21 can be made small and a part of the horizontal micro program can be stored. In the case of changing only the field, the effect of reducing the gate amount becomes large.

[0026]

As described above, according to the present invention, since the control memory is constituted by combining the ROM and the RAM, there is an effect that it is possible to change the microprogram and reduce the gate amount.

[Brief description of drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention.

FIG. 2 is a block diagram of a second embodiment of the present invention.

FIG. 3 is a block diagram of a third embodiment of the present invention.

[Explanation of symbols]

 1, 10 Main control memory 2, 20, 21 Sub control memory 3 Address register 4 Selector 5 Address match detection circuit 6 Effective flag memory circuit 7 Decoder

Claims (3)

[Claims] 1. A main control memory composed of a ROM storing a main microprogram composed of microinstructions, and a RAM storing a submicroprogram composed of a microinstruction and an address of the main control memory. Was
And its address is associated with one of the addresses of the main control memory, the sub-control memory being read simultaneously with the main control memory, the address of the main control memory and the main control memory read from the sub-control memory. Address match detection means for comparing the addresses of the control memory, and as a result of this comparison, if no match is detected, the microinstruction read from the main control memory is selected, and if a match is detected, the micro instruction is selected. A control memory comprising: a selecting unit for selecting a microinstruction read from the sub-control memory. 2. The sub-control memory stores the sub-microprogram, and instead of the address coincidence detecting means, stores a valid flag indicating whether each step of the main control memory is valid or invalid. In the case of providing a valid flag storage means that is read at the same time as the main control memory, selecting the micro instruction read from the main control memory when the read valid flag indicates valid, and indicating invalid 2. The control memory according to claim 1, wherein a microinstruction read from the sub-control memory is selected as the sub memory. 3. The main control memory stores a horizontal microprogram for executing a plurality of microinstructions in one step, and the subcontrol memory stores one microinstruction and its subfield position information. Storing a micro program, and replacing the selector with a number equal to the number of micro instructions for selecting one of the plurality of micro instructions and one of the micro instructions read from the sub-control memory The number of selectors is the same as the number of microinstructions read from the main control memory when the read valid flag indicates that the valid flag is valid. The microinstruction read out from the sub control storage only for the field is selected by the selector. 2 control store according.