JPH04282734A - Cache memory control device - Google Patents

Abstract

PURPOSE:To improve a pit rate by distinguishing local data for a user program from global data shared between programs and properly using a cache memory. CONSTITUTION:A specification pit for specifying which memory circuit means out of plural memory circuit means 11 registers a corresponding page is set up in a page table entry for executing virtual address conversion and the cache memory or a ROM for registering data in each virtual address page is selected and used in accordance with the contents of the specification pit. For instance, kernel codes in an operating system are allocated to the ROM and data or instructions other than the kernel codes are allocated to the cache memory. Since the storage area of the kernel codes of the operating system is usually different from that of the user program, the cache memory is efficiently used and the pit rate, is improved by dividing respective data or instructions and registering them in the cache memory or the ROM.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION The present invention is used to control multiple types of cache memories. The present invention relates to a cache memory control device that operates with a processor that employs a virtual address method.

0002

2. Description of the Related Art Conventionally, in control systems for a plurality of types of cache memories of this type, there has been a distinction between instructions and operands.

0003

[Problems to be Solved by the Invention] In conventional cache memory control systems, there is a distinction between instruction cache memory and data cache memory as multiple types of cache memory, and cache memory is developed by focusing on the fact that the locality of memory access is different for each type of cache memory. were used separately to improve the hit rate. However, in this type of cache memory control method, the data registered in the data cache memory does not distinguish between local data specific to a process and global data shared between processes, and the data in the data cache memory is uniformly distributed. was being treated. The locality of memory access is different for these local and global data, and it is possible to improve the hit rate by registering them in separate data cache memories, but this is not possible with conventional methods, and Cache memory stores user program instructions and operating system kernel code, but even if you try to improve the hit rate of cache memory by distinguishing these and using separate instruction cache memories, conventional cache There is a problem in which this cannot be easily achieved with the memory control method.

[0004] The present invention is intended to solve such problems, and an object thereof is to provide a device that can improve the hit rate of a cache memory.

[0005]

[Means for Solving the Problems] The present invention includes a processor that employs a virtual address system, and memory circuit means including a plurality of types of cache memory circuits and a plurality of types of ROM circuits. In a cache memory control device in which a circuit and the ROM circuit are connected by an address signal means and a bidirectional data signal means, a page table entry for performing virtual address conversion indicates that a corresponding page is connected to the cache memory circuit and the ROM circuit. A memory circuit means specification bit is provided to specify in which memory circuit the memory circuit is registered, and when the memory circuit means is accessed, the processor selects the plurality of types of cache memory circuits and the above according to the contents of the memory circuit means specification bit. Each of the ROM circuits is provided with a memory circuit means selection transmission signal means for notifying that the memory circuit has been selected, and the cache memory circuit is hit only when selected by the memory circuit means selection transmission signal means. outputting a miss-hit determination result via a hit-miss-hit result signal means;
the ROM circuit includes means for outputting read data to the data signal means; the ROM circuit includes means for outputting read data to the data signal means only when selected by the memory circuit means selection transmission signal means; At the time of memory read, the signal from the hit-miss-hit result signal means sent by the plurality of cache memory circuit means is input, and the timing at which read data from the cache memory circuit is determined is determined for the processor based on the signal. The present invention is characterized by comprising a plurality of cache memory control units that transmit the cache memory read timing through a cache memory read timing transmitting means.

[0006] A page table entry for performing virtual address conversion is provided with a memory circuit means specification field for specifying information indicating in which memory circuit of the cache memory circuit and the ROM circuit the corresponding page is registered in a code. , comprising decoding circuit means for receiving the contents of the memory circuit means specification field from the processor and decoding which memory circuit means is selected, and outputting the decoding result of the decoding circuit means to the memory circuit means selection transmission signal means. The cache memory control section may include means for temporarily stopping the operation of the processor in the event of a miss based on an input signal from the hit/miss hit result signal means. desirable.

[0007]

[Operation] A designation bit is provided on the page table entry that performs virtual address conversion to specify which of the multiple memory circuit means the corresponding page is registered in, and the virtual address is changed according to the contents of this designation bit. Select and use the cache memory and ROM registered in page units.

For example, the kernel code of an operating system is allocated to ROM, and other data or instructions are allocated to cache memory. Normally, the kernel of the operating system and the user program are stored in different areas, so by dividing them and registering instructions or data in the cache memory and ROM, the cache memory can be used efficiently and the hit rate can be improved. will improve.

In the case of multiple types of ROMs, for example, interrupt processing programs that require responsiveness can be resident in multiple types of ROMs to improve the real-time performance of the operating system. Further, as an effect of using multiple types of cache memory, for example, an example in which the instruction cache memory is used separately for the user program and the kernel of the operating system can be considered. Allocate cache memory in the page entry of the user program, and allocate other cache memory in the kernel. If the areas of memory accessed by the user program and the kernel are significantly different, and if there are frequent switches between the user and the kernel, using separate cache memories like this can improve the hit rate. can.

[0010] Another example is to maintain the consistency of cache memory contents in a multiprocessor by distinguishing between data local to a user program and global data shared between programs and using the cache memory accordingly. The amount of required hardware can be reduced. A multiprocessor cache memory usually requires a mechanism to compare bus operations with data registered in the cache memory for the purpose of maintaining consistency, but by dividing the data cache memory into local and global areas, consistency This means that it is only necessary to provide a comparison hardware mechanism for the global data cache memory, for which performance should be a concern. Furthermore, since the locality of memory access is different between local and global, the hit rate can be improved by dividing the data cache memory into local and global.

[0011]

Embodiments Next, embodiments of the present invention will be explained based on the drawings. In order to simplify the explanation, this embodiment will be described using an example including only one each of a plurality of types of cache memory circuits and one ROM circuit.

(First Embodiment) FIG. 1 is a block diagram showing the configuration of a first embodiment of the present invention.

The first embodiment of the present invention includes a processor 1 employing a virtual address system, and memory circuit means 11 including a plurality of types of cache memory circuits 3 and a plurality of types of ROM circuits 4. The memory circuit 3 and the ROM circuit 4 are connected by an address signal means 6 and a bidirectional data signal means 5, and as a feature of the present invention, a page corresponding to a page table entry for which virtual address conversion is performed is connected to a cache memory circuit. A memory circuit means designation bit is provided to designate which memory circuit of the 3 and ROM circuit 4 the data is registered in, and when the memory circuit means 11 is accessed, multiple types of data are sent from the processor 1 according to the contents of the memory circuit means designation bit. Each of the cache memory circuit 3 and the ROM circuit 4 is provided with a memory circuit means selection transmission signal means 7 which informs that the memory circuit has been selected. includes means for outputting a hit-miss-hit judgment result via a hit-miss-hit result signal means 8 and outputting read data to the data signal means 5 only when the result is a hit-miss-hit, and transmits memory circuit means selection to the ROM circuit 4. It includes means for outputting read data to the data signal means 5 only when selected by the signal means 7, and receives signals from the hit-miss-hit result signal means 8 sent by the plurality of cache memory circuits 3 when reading the cache memory. a plurality of cache memory control units 2 which transmit the timing at which read data from the cache memory circuit 3 is finalized to the processor 1 via a cache memory read timing transmission means 9 based on the input signal; The cache memory control unit 2 is configured to control the processor 1 at the time of a miss based on the input signal from the hit/miss hit result signal means 8.
including means for temporarily suspending the operation of the

In reality, the cache memory circuit 3 includes a data array, an address array, a hit/miss hit detection circuit, a cache memory read/write control unit, etc. Although control signal lines such as lights are provided, they are omitted in this embodiment.

Next, the operation of the first embodiment of the present invention constructed as described above will be explained.

FIG. 2 is a diagram showing the format structure of a page table entry for virtual address translation in the first embodiment of the present invention. Two bits in this page table entry are cache memory circuit means designation bits, and only one of these bits is always set to '1'. If the page corresponding to the entry is registered in the cache memory (1), the memory circuit means designation bit (1) shown in FIG. 2 is set to '1'. The corresponding page is RO
When stored in M(1), the memory circuit means designation bit (2) is '1'.

The processor 1 supports virtual addresses and refers to an address conversion page table when accessing the cache memory. Further, when the cache memory circuit means 3 and the ROM circuit means 4 are accessed using physical addresses, a page table is used to convert the logical address into a physical address upon memory access. At this time, the processor 1 refers to the memory circuit means designation bit of the page table entry and transmits the value to the cache memory (1) by the memory circuit means selection transmission signal means 7.
) and ROM (1).

Here, if the value of the memory circuit means designation bit (1) in the page table entry is '1', the cache memory (1) determines that it has been selected from the contents of the memory circuit means selection transmission signal means 7. Judging,
Only cache memory (1) is accessed. At this time, the cache memory (1) determines whether it is a hit or miss, and notifies the cache memory control unit 2 of the result using the hit-miss-hit result signal means 8. If there is a miss, the cache memory read timing transmitting means 9 causes the processor 1 to wait until the necessary data reaches the cache memory circuit 3 from the ROM circuit 4.

When the value of the memory circuit means designation bit (2) is '1', the memory circuit means selection transmission signal means 7 notifies that the ROM (1) has been selected, and the ROM
(1) The data is output to the data signal means 5.

When a plurality of types of cache memory circuit means are included, a plurality of circuit means corresponding to the cache memory circuit means 3 are connected to the data signal means 5 and the address signal means 6, and the cache memory control means 2 is connected to a plurality of circuit means corresponding to the cache memory circuit means 3. Hit/miss/hit result signal means 8 from the cache memory is input, and if any of them is a miss, control is performed to make the processor 1 wait.

When a plurality of types of ROM circuit means are included, the circuit means corresponding to the ROM circuit 4 is connected to a plurality of data signal means 5 and address signal means 6. In this case, the designation bits of the page table entry shown in FIG. 2 are also increased to correspond to the plurality of types of memory circuit means.

(Second Embodiment) Next, a second embodiment of the present invention will be described with reference to the drawings. FIG. 3 is a block diagram showing the configuration of a second embodiment of the present invention. Similar to the first embodiment, this second embodiment will be described using an example including only one each of a plurality of types of cache memory circuits and one ROM circuit to simplify the explanation.

In the second embodiment of the present invention, information indicating in which memory circuit of the cache memory circuit 3 and the ROM circuit 4 the corresponding page is registered is specified in a code in a page table entry for performing virtual address translation. a memory circuit means designation field for receiving the content of the memory circuit means designation field from the processor 1 and decoding circuit means 10 for decoding which memory circuit is selected; The second embodiment includes means for transmitting the decoding result output of the decoding circuit means 10 to each of the memory circuit means 11, and is otherwise constructed in the same manner as the first embodiment.

The decoding circuit means 10 provided in this second embodiment decodes the memory circuit means designation field outputted from the processor 1, and sends the result to the cache memory circuit via the memory circuit means selection transmission signal means 7. 3 and ROM circuit 4.

FIG. 4 is a diagram showing the format structure of the corresponding page table entry for virtual address translation in the second embodiment of the present invention. One of the bits is the memory circuit means specification field, and the '0' or '1' in that field bit indicates whether the corresponding page is registered in the cache memory (1) or the ROM (1). It is expressed as the value of The decoding circuit means 10 shown in FIG. 3 interprets that the cache memory (1) is selected when this field bit is '0', and that the ROM (1) is selected when this field bit is '1'. This is interpreted as such and is transmitted to the cache memory circuit 3 and ROM circuit 4 via the memory circuit means selection transmission signal means 7.

When there are multiple types of cache memory circuit means or multiple types of ROM circuit means, the page table entry designation field in FIG. For example, it is expanded to 2 bits for two types of cache memory and two types of ROM.

[0027]

[Effects of the Invention] As explained above, according to the present invention, cache memory can be used efficiently.
Hit rate can be improved. In addition, multiple types of R
In the case of OM, the real-time performance of the operating system can be improved. Furthermore, by using different cache memories, it is possible to reduce the amount of hardware required to maintain the consistency of the contents of the cache memory.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a first embodiment of the present invention.

FIG. 2 is a diagram showing the format structure of a page table entry for virtual address translation in the first embodiment of the present invention.

FIG. 3 is a block diagram showing the configuration of a second embodiment of the present invention.

FIG. 4 is a diagram showing a format configuration of a page table entry for virtual address translation in a second embodiment of the present invention.

[Explanation of symbols]

1 Processor 2 Cache memory control section 3 Cache memory circuit 4 ROM circuit 5 Data signal means 6 Address signal means 7 Memory circuit means selection transmission signal means 8
Hit miss hit result signal means 9 Cache memory read timing transmitting means 10 Decoding circuit means 11 Memory circuit means

Claims (3)

[Claims] Claim 1: A processor that employs a virtual address system, multiple types of cache memory circuits, and multiple types of R
A cache memory control device comprising memory circuit means including an OM circuit, wherein the processor, the cache memory circuit, and the ROM circuit are connected by address signal means and bidirectional data signal means, in which virtual address conversion is performed. In the page table entry, the corresponding page is stored in the cache memory circuit and the RO.
A memory circuit means designation bit is provided to designate in which memory circuit of M circuits the memory circuit is registered, and when the memory circuit means is accessed, the plurality of types of cache memory are selected from the processor according to the contents of the memory circuit means designation bit. memory circuit means selection transmission signal means for informing each of the circuit and the ROM circuit that the memory circuit has been selected; the ROM circuit includes means for outputting a hit-miss-hit determination result via the hit-miss-hit result signal means, and outputting read data to the data signal means, and transmits the selected data to the ROM circuit by the memory circuit means selection transmission signal means. includes means for outputting the read data to the data signal means only when the read data is read, and inputs the signal from the hit-miss-hit result signal means sent by the plurality of cache memory circuit means when reading the cache memory; A cache memory control comprising a plurality of cache memory control units configured to transmit the timing at which read data from the cache memory circuit is finalized to the processor via a cache memory read timing transmitting means based on a signal. Device. 2. A memory circuit means specification field that specifies, in a code, information indicating in which memory circuit of the cache memory circuit and the ROM circuit the corresponding page is registered in a page table entry for performing virtual address conversion. further comprising decoding circuit means for receiving the contents of the memory circuit means specification field from the processor and decoding which memory circuit means is selected, and the memory circuit means selection transmission signal means;
2. A cache memory control device according to claim 1, further comprising means for transmitting a decoding result output of said decoding circuit means to each of said memory circuit means. 3. The cache memory control device according to claim 1, wherein said cache memory control section includes means for temporarily stopping the operation of said processor upon a miss based on an input signal from said hit/miss hit result signal means.