JPH05210582A - Cache memory control system - Google Patents

Abstract

PURPOSE:To improve the hit rate by using plural cache memories, specifying local and global data in the respective cache memories and a ROM according to an address conversion table, and shortening a selection time. CONSTITUTION:This cache memory control system consists of a processor 1 which has the page table for virtual address conversion internally in the data cache memories and controls the whole device, a cache memory circuit part 3, a ROM circuit part 4, a two-way bus 5, an address signal line 6, etc. Then when the cache memory circuit specification bit of the address conversion page table stored internally in the processor 1 is '1', the cache memory circuit part 3 judges that the cache memory circuit part 3 itself is selected and only the cache memory circuit part 3 is accessed. Similarly, when the ROM circuit specification bit of the address conversion page table is '1', it is informed through a memory select signal line 7 that the ROM circuit part 4 is selected, and data of the ROM circuit part 4 are outputted to the two-way bus 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache memory control system, and more particularly to a cache memory control system for a plurality of types of cache memories operating with a processor adopting a virtual address system.

[0002]

2. Description of the Related Art Conventionally, this type of cache memory control system has a distinction between an instruction cache memory and a data cache memory as a plurality of types of cache memories.
Focusing on the difference in the locality of memory access, we tried to improve the hit rate by using the cache memory separately.

In the data cache memory, local data unique to a process (hereinafter referred to as local data) and global data shared between processes (hereinafter referred to as global data) are registered as data. Is treated like.

Further, the instruction cache memory stores the instructions of the user program and the kernel code of the OS for uniform handling.

[0005]

In the conventional cache memory control method described above, since local / global data is registered in the same data cache memory, there is a problem in that selection takes time and the hit rate is not improved. is there.

Further, since the instruction of the user program and the kernel code of the OS are registered in the same instruction cache memory, there is a problem that the selection takes time and the hit rate is not improved.

[0007]

A cache memory control system according to the present invention is a cache memory circuit which is a cache memory including a data array, an address array, a hit / miss hit detection circuit, and a read / write control unit for storing first data. Section, a ROM circuit section which is a ROM for storing second data having a different type from the first data and including a data array, an address array, and a read control section, and a corresponding page are registered in the cache memory circuit section. There is a 2-bit portion including a 1-bit cache memory circuit designating bit that indicates that there is one bit and a 1-bit ROM circuit portion designating bit that indicates that it is registered in the ROM circuit portion. Built-in address translation page table for virtual address translation where "1" is A processor for controlling the entire port to the equipment, the processor and the cache memory circuit portion,
A bidirectional bus connecting the ROM circuit section, an address signal line for transmitting an address signal output from the processor to the cache memory circuit section and the ROM circuit section, and a cache memory circuit section and the ROM from the processor
A memory select signal line for transmitting a memory select signal output to a circuit section, a hit miss hit result signal line for transmitting a hit miss hit result signal output from the cache memory circuit section, and the hit miss hit result signal. It has a cache memory control unit which receives and outputs a cache memory read timing signal to the processor, and a cache memory read timing signal line which transmits the cache memory read timing signal to the processor.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described with reference to the drawings. FIG. 1 is a block diagram of the first embodiment of the present invention. The present invention is a data cache memory, which includes a processor 1 for controlling the entire apparatus by incorporating a page table for virtual address conversion, a cache memory circuit unit 3 which is a cache memory for storing local data, and global data. ROM circuit section 4 which is a ROM, processor 1, cache memory circuit section 3, ROM circuit section 4
A two-way bus 5 for connecting the two, an address signal line 6 for transmitting an address signal output from the processor 1 to the cache memory circuit section 3, the ROM circuit section 4, and the processor 1
From the cache memory circuit section 3 to the ROM circuit section 4 from the memory selection signal line 7
And a hit-miss-hit result signal line 8 for transmitting the hit-miss-hit result signal output from the cache memory circuit section 3, and a cache memory for receiving the hit-miss-hit result signal and outputting a cache memory read timing signal to the processor 1. It is composed of a control unit 2 and a cache memory read timing signal line 9 for transmitting a cache memory read timing signal to the processor 1.

The cache memory circuit unit 3 includes a data array, an address array, a hit / miss hit detection circuit, a read / write control unit, etc., which are not shown. Further, between the processor 1 and the cache memory, control signals such as read / write as in the normal cache memory are omitted. The ROM circuit unit 4 includes a data array, an address array, a read control unit and the like, which are not shown. Also, the processor 1, cache memory, and ROM
In the meantime, control signals such as ordinary cache memory and read / write similar to ROM are omitted.

FIG. 2 is an explanatory diagram showing an example of an entry format of the address translation page table for virtual address translation of the processor shown in FIG. The address translation page table 20 a has a 1-bit cache memory circuit section designating bit 11 indicating that the corresponding page is registered in the cache memory circuit section 3 and 1 indicating that the page is registered in the ROM circuit section 4. ROM for bits
It has two bits corresponding to the circuit section designation bit 12, and only one of them is always "1".

Next, the operation of the embodiment will be described.
The processor 1 supports virtual addresses, and refers to the address translation page table 20a when accessing the cache memory. Further, if the cache memory circuit unit 3 and the ROM circuit unit 4 are physical cache memories, the logical address is converted into a physical address using the address conversion page table 20a when accessing the cache memory. At this time, the processor 1 refers to the cache memory circuit section designating bit 11 or the ROM circuit section designating bit 12 and outputs the value to the cache memory circuit section 3 and the ROM circuit section 4 through the memory selection signal line 7.

Assuming that the value of the cache memory circuit section designation bit 11 is "1", the cache memory circuit section 3
Judges that it has been selected from the contents notified via the memory selection signal line 7, and the cache memory circuit unit 3
Only is accessed. At this time, the hit-miss-hit is judged only by the cache memory circuit unit 3, and the result is notified to the cache memory control unit 2 via the hit-miss hit result signal line 8. If there is a mishit here, the cache memory control unit 2 causes the processor 1 to wait on the cache memory read timing signal line 9 until the local data reaches the cache memory from the memory. Similarly, when the value of the ROM circuit section designation bit 12 is “1”, it is notified via the memory selection signal line 7 that the ROM circuit section 4 has been selected, and the global data of the ROM circuit section 4 is bidirectional. It is output to the bus 5.

Next, a second embodiment of the present invention will be described with reference to the drawings. FIG. 3 is a block diagram of the second embodiment of the present invention. The present invention has a configuration in which a decoding circuit 10 is provided between the processor 1 and the memory selection signal line 7. The decoding circuit 10 decodes the memory circuit section designation field output from the processor 1, and transmits the result to the cache memory circuit section 3 and the ROM circuit section 4 via the memory selection signal line 7.

FIG. 4 is an explanatory diagram showing an example of an entry format of the address translation page table for virtual address translation of the processor shown in FIG. The address translation page table 20b has a 1-bit memory circuit section designation field 13 instead of the 2-bit cache memory circuit section designation bit 11 and the ROM circuit section designation bit 12 included in the page table entry 20a of FIG. Have If the value of the memory circuit section designating field 13 is "0", the decode circuit 10 causes the cache memory circuit section 3
Is selected, and if this value is “1”, it is interpreted that the ROM circuit unit 4 is selected, and that effect is notified via the memory selection signal line 7 to the cache memory circuit unit 3 and the ROM circuit unit 4. Communicate with.

In the above-described first embodiment, the local data is stored in the cache memory circuit section 3 as the first data and the global data is stored in the ROM circuit section 4 as the second data. It is also possible to change the first data into global data and the second data into local data.

Further, in the above-mentioned first embodiment, the present invention can be used in the instruction cache memory, and the first data can be set as the instruction of the user program and the second data can be set as the kernel code of the OS. Is. It is also possible to set the first data to the kernel code of the OS and the second data to the instruction of the user program.

In the first embodiment described above, R
When the value of the OM circuit section designating bit 12 is "0", the ROM circuit section 4 is selected, and when the value of the cache memory circuit section designating bit 11 is "0", the cache memory circuit section 3 is selected. It is also possible to change as follows.

Also, in the second embodiment, if the value of the memory circuit section designation field 13 is "0", the ROM circuit section 4
It is also possible to change so that the cache memory circuit unit 3 is selected when the value of the memory circuit unit designation field 13 is “1”.

As described above, according to the present invention, a plurality of cache memories are used, and local / global data is designated in each cache memory and ROM in the address translation page table to shorten the selection time. There is an effect that the rate can be improved.

Further, the instructions of the user program and the kernel code of the OS are respectively stored in the cache memory and the R memory.
There is an effect that the hit rate can be improved by designating the OM and shortening the selection time.

[Brief description of drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention.

2 is an explanatory diagram showing an example of an entry format of an address translation page table for virtual address translation of the processor shown in FIG. 1. FIG.

FIG. 3 is a block diagram of a second embodiment of the present invention.

4 is an explanatory diagram showing an example of an entry format of an address translation page table for virtual address translation of the processor shown in FIG.

[Explanation of symbols]

 1 processor 2 cache memory control unit 3 cache memory circuit unit 4 ROM circuit unit 5 bidirectional bus 6 address signal line 7 memory selection signal line 8 hit miss hit result signal line 9 cache memory read timing signal line 10 decode circuit 11 cache memory circuit Part designation bit 12 ROM circuit part designation bit 13 Memory circuit part designation field 20a, 20b Address conversion page table

Claims (3)

[Claims] 1. A cache memory circuit unit which is a cache memory for storing first data including a data array, an address array, a hit / miss hit detection circuit, and a read / write control unit, and a data array, an address array, and a read control unit. A ROM circuit unit that is a ROM that stores second data of a different type from the first data that is included, and a cache memory circuit unit designation for 1 bit that indicates that the corresponding page is registered in the cache memory circuit unit. For virtual address conversion, it has two bits, one bit indicating that the bit is registered in the ROM circuit section and one bit indicating the ROM circuit section, and only one of these bits is "1". A processor that has a built-in address translation page table and supports virtual addresses to control the entire device; Cessa and cache memory circuit part,
A bidirectional bus connecting the ROM circuit section, an address signal line for transmitting an address signal output from the processor to the cache memory circuit section and the ROM circuit section, and a cache memory circuit section and the ROM from the processor
A memory select signal line for transmitting a memory select signal output to a circuit section, a hit miss hit result signal line for transmitting a hit miss hit result signal output from the cache memory circuit section, and the hit miss hit result signal. A cache memory control method comprising: a cache memory control unit that receives and outputs a cache memory read timing signal to the processor; and a cache memory read timing signal line that transmits the cache memory read timing signal to the processor. .. 2. When the processor converts a logical address into a physical address and the cache memory circuit unit and the ROM circuit unit are physical cache memories, the cache memory circuit unit of the address conversion table is used when accessing the cache memory. Specified bit or ROM
When the value of the cache memory circuit designating bit is “1”, the value is output to the cache memory circuit unit and the ROM circuit unit through the memory selection signal line with reference to the circuit unit designating bit. The unit judges that it has been selected, determines a hit-miss hit, and notifies the result to the cache memory control unit via the hit-miss hit result signal line. If the read timing signal line causes the processor to wait, and if there is no mistake, the first data is output to the bidirectional bus. When the value of the ROM circuit designating bit is "1", the ROM circuit is self 2. The cache memory control method according to claim 1, wherein the second data is output to the bidirectional bus when it is determined that it has been selected. 3. A 2-bit cache memory circuit section designating bit and R included in the address translation page table
The OM circuit section designating bit is changed to a memory circuit section designating field for 1 bit, and the memory circuit section designating field is decoded between the processor and the memory selection signal line to obtain the memory circuit section designating field bit. Is "0" or "1", either the cache memory circuit section or the ROM circuit section is selected, and the fact is transmitted to the cache memory circuit section or the ROM circuit section via the memory selection signal line. 3. The cache memory control system according to claim 1, further comprising a decoding circuit for performing the above.