JPH01261768A - Data communication system - Google Patents

Abstract

PURPOSE:To improve the reliability of data only by executing memory access operation simply from a destination to be communicated to read out data from a communicating source. CONSTITUTION:At the time of generating a communication request between information processors 11, 12, writing data are written in an address sent from a requesting information processor 11 to a memory 2. When a communicated code including information for informing the writing of writing data in the memory 2 and an address are sent, the information processor 12 to be communicated reads out the writing data from the memory 2 by a memory access. Consequently, inter-information processor communication having highly reliable writing data, wide communication data width and simple structure can be attained.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data communication system, and more particularly to a data communication system in which data communication between information processing devices is performed via a common memory.

In this type of conventional data communication system, a memory control device is used to control data communication between a plurality of information processing devices. This type of memory control device generally performs data communication control mainly in the following two modes.

In the first mode, communication data is set in memory in advance, the existence of the communication data is notified to other information processing devices by an interrupt signal, and the processing device of the relevant function processes the communication data without reading it. The devices are designed to communicate with each other.

In the second mode, the address signal to the memory is also used as communication data, and the address signal is sent to another processing device to perform communication.

In such conventional data communication between processing units, since the communication data is written in memory in advance, the data must be read from the memory during communication between processing units before the memory can be used for the next communication. It cannot be rewritten. Therefore, if a communication request between processing units cannot be sent due to an error etc. after writing to the memory, the written data in the memory (
The disadvantage is that the communication data (communication data) may become fraudulent.

In particular, in the second mode, since the memory address is used as write data during communication between devices, the bit width becomes narrow and there is a drawback that a large amount of data cannot be sent. Another drawback is that memory access to arbitrary addresses is not possible.

SUMMARY OF THE INVENTION The purpose of the present invention is to provide a data communication method that improves the reliability of data by reading data from a communication source by simply performing a memory access operation from the communication destination. be.

Another object of the present invention is to freely control the write address to the memory so that the communication data from the communication source is written sequentially, and the communication destination reads this asynchronously and sequentially, even when the amount of data is large. ,correct.

The purpose of the present invention is to provide a data communication method that enables flexible communication.

Hokusobori 1 According to the present invention, there is provided a data communication method in which data communication between a plurality of information processing devices is performed via a memory provided in common to these information processing devices, A writing means for writing communication data from a request source during inter-device communication to a write address from the request source in the memory, and means for notifying the communication partner of the write address in the memory, A data communication system is obtained in which the communication partner accesses the write address and reads the written data in response to this notification.

K-Otori” Embodiments of the present invention will be described below with reference to the drawings.

The figure is a system block diagram of an embodiment of the present invention. In figure 0, two information processing devices 1 are connected to a common memory 2.
1 and 12 are provided, and these devices 11 and 1
2 shows a case where data communication is performed between the two via the common memory 2.

A memory control device 3 is provided corresponding to the information processing device 11, and a boat address register 31 receives the address of the memory 2 during inter-device communication.

The boat request code register 32 receives the request contents of the processing request. The boat write data register 33 receives write data sent from the information processing device 101.
The communication destination code reception register 34 receives the communication destination code sent from the information processing device 11.

The decoder 35 decodes the output of the request code. The memory write command 36 generates a memory write command during communication between devices. Selector 37 is decoder 35
The address sending register 38 selectively derives a memory access request and an inter-device communication request according to the decoded output of the address sending register 38 sends a write address of write data to the memory 2 and the information processing device 12. The three memory request command registers send processing requests to the memory 2. The inter-device communication request sending register 40 sends an inter-device communication request to the information processing device 12. The memory write data sending register 41 sends write data to the memory 2. The communication destination code sending register 42 sends the communication destination code to the information processing device 11.

Next, the operation of the memory control device 3 shown in the figure will be explained. During inter-device communication, the information processing device 11 sets an address, a request code, and a write data communication destination code in each of the boat registers 31 to 34, respectively. The set boat address register 31 is set in the address sending register 38, and becomes the write address for write data to the memory 2. The data set in the boat request code register 32 passes through the decoder 35 and controls the selector 37. This selector 37 sets the memory write command 36 in the memory request command register 39, and sends it as a memory write access request for the memory 2.

The data set in the boat write data register 33 is set in the memory write data sending register 41 and written to the memory 2.0 The communication destination code set in the communication destination code reception register 34 is the communication destination code sending register. 42, and the set communication destination code is sent to the information processing device 12 together with the inter-device communication request set in the inter-device communication request sending register 40 and the address set in the address sending register 38. Sent out.

The information processing device 12 that received the inter-device communication request accesses the memory according to the sent address and stores the memory 2.
The inter-device communication data is read from the . Although data reading is not explicitly shown in the figure, its configuration is self-evident, so it is omitted.

When performing data communication from the information processing device 12 to the information processing device 11, a memory control device (not shown) provided corresponding to the information processing bag rI 112 (same configuration as shown) is used to perform similar processing. be done. It is clear that the present invention is similarly applicable to a case where there are three or more information processing apparatuses.

1.1 As explained above, according to the present invention, when a communication request is issued between information processing devices, write data is written to the memory at the address sent from the requesting information processing device. The communication destination code and address containing information to notify that write data has been written to the memory are sent to the information processing device indicated by the communication destination address, thereby transmitting the communication destination information. By reading the write data from the memory through memory access, the processing apparatus has the advantage that the reliability of the write data is high, the communication data width is wide, and the communication between the information processing apparatuses can be performed with a simple structure.

[Brief explanation of the drawing]

The figure is a block diagram of an embodiment of the invention. Explanation of symbols of main parts 2...Memory 3...Memory system 6iI device 11.12...Information processing device 31...Boat address register 32...・・・
...Boat request code register 33...
Boat write data register 34...Communication destination code reception register 35...Decoder

Claims (1)

[Claims] (1) A data communication method in which data communication between multiple information processing devices is carried out via a memory provided in common to these information processing devices, in which data communication from a request source is performed during communication between information processing devices. Write means for writing communication data to a write address from the request source in the memory, and means for notifying the write address in the memory to the communication partner, and in response to this notification, the communication partner The data communication method is characterized in that written data is read by accessing the write address.