JPH04367043A - Memory controller - Google Patents

Abstract

PURPOSE:To obtain a memory control circuit which can give the continuous addresses to each memory board without changing the circuit of a decoder when the memory capacity is changed or the order of memory boards is changed. CONSTITUTION:The memory capacity recognizing means 44a, 46a, 48a, ... recognize the capacity of the loaded memory boards 44, 46 48, ..., and output the recognized capacity as a recognition signal 68. A decoder 42 receives the more significant bits 60 and 62 to decode them and outputs a selection signal 66 to show one of those memory boards to be selected. Then the decoder 42 works after changing the decoding mode in response to the signal 68 received from each memory capacity recognizing means. Therefore the continuous addresses can be applied to the boards 44, 46, 48,... without changing the circuit of the decoder 42.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory control device, and more particularly to control of a plurality of memory boards having different capacities.

0002

2. Description of the Related Art When a large capacity memory area is required in a digital circuit system, a memory board with a certain capacity is formed using memory elements or modules.
These are managed as a collection of memory boards. moreover,
If there are multiple memory boards with different memory capacities, it is necessary to manage the addresses of each memory board.

FIG. 6 shows a configuration diagram of a conventional memory control device. This memory control device includes a CPU 10, a decoder 1
2. It is composed of memory boards 14, 16, 18, . . . Note that the upper two bits 30 of the address signal are sent from the CPU 10 to the decoder 12. next top 2
Bit 32 is sent from CPU 10 to decoder 12 and memory boards 14, 16, 18, . The next most significant bit is used according to the memory capacity. The lower bit 34 of the address signal is transmitted from the CPU 10 to the memory board 1.
4, 16, 18, etc. Further, the selection signal 36 is transmitted from the decoder 12 to the memory boards 14, 16, 1
Sent to 8,...

FIG. 7 shows a table of the decoder 12 of FIG. 6. In this example, the memory is 4M memory board 14
, 1M memory board 16, 1M memory board 18,
It is composed of 4M memory boards 20, . Further, the upper bit 30 and the next upper bit 32 of the address signal represent (■■■■). As shown in this figure, the addresses range from (0000...) to (0011.
), the decoder 12 is set to output H as the selection signal 36 to the memory board 14. Therefore, the CPU 10 uses the address (0000...
) to (0011...), memory board 1
4.

Next, when the address is (0100...), the decoder 12 is set to output H as the selection signal 36 to the memory board 16. Therefore, when the CPU 10 sends out an address (0100...), it is mapped to the memory board 16. below,
Similarly mapped.

[0006] In this way, memory mapping has been performed by setting the decoder in advance in accordance with the memory capacity of each memory board.

[0007]

However, due to design changes, there may be cases where it is desired to replace the memory board with a memory board of a different capacity or to change the order of the memory boards. In this case, the decoding method described above has the problem that the addresses of the memory board become discontinuous and the memory usage efficiency decreases, so that it is necessary to change the decoder circuit.

An object of the present invention is to solve the above problems and realize a memory control circuit that does not require modification of the decoder.

[0009]

[Means for Solving the Problem] A memory control circuit according to claim 1 is a memory control device that controls a plurality of memory boards having different memory capacities. The memory capacity recognition means receives the upper bit of the address signal, decodes it, and outputs a selection signal indicating which memory board to select. The apparatus includes a decoder that changes and operates according to the recognition signal from the recognition means.

[0010] The memory control circuit according to the second aspect of the present invention is a memory capacity recognition device that recognizes the capacity of an attached memory board and outputs the capacity as a recognition signal in a memory control device that controls a plurality of memory boards having different memory capacities. means, recognition signal storage means for storing the recognition signal output from the memory capacity recognition means, receiving the upper bit of the address signal, decoding it, and outputting a selection signal indicating which memory board to select. The apparatus further includes a decoder that operates by changing the mode of decoding according to the recognition signal from the recognition signal storage means.

[0011]

In the memory control circuit according to the first aspect of the present invention, the memory capacity recognition means recognizes the capacity of the attached memory board and outputs the capacity as a recognition signal. The decoder receives the upper bit of the address signal, decodes it, and outputs a selection signal indicating which memory board to select, and the decoding mode is determined by the recognition signal from each memory capacity recognition means. It works by changing it accordingly. Therefore, consecutive addresses can be given to each memory board without changing the decoder circuit.

[0012] In the memory control circuit according to the second aspect, the memory capacity recognition means recognizes the capacity of the attached memory board;
The capacitance is output as a recognition signal. The recognition signal storage means stores the recognition signal output from the memory capacity recognition means. The decoder receives the upper bit of the address signal, decodes it, and outputs a selection signal indicating which memory board to select, and the decoding mode is determined based on the recognition signal from the recognition signal storage means. Change it accordingly and it will work. Therefore, consecutive addresses can be given to each memory board without changing the decoder circuit and even if the memory board does not have a hardware memory capacity recognition means.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a configuration diagram of a memory control device which is an embodiment of the present invention. This memory control device is a CPU
40, decoder 42, memory board 44, 46, 48,
. . , ID bits 44a, 46a, 48a, . . . are memory capacity recognition means added to the memory board. Note that the upper two bits 60 of the address signal are connected from the CPU 40 to the decoder 42. The next upper two bits 62 are sent from the CPU 40 to the decoder 4.
2 and memory boards 44, 46, 48, . The next most significant bit is used according to the memory capacity. The lower bit 64 of the address signal is
are connected to memory boards 44, 46, 48, . Furthermore, the recognition signal 66 is sent to the decoder 42 from the memory capacity recognition means 44a, 46a, 48a, . The selection signal 68 is sent from the decoder 42 to the memory boards 44, 46, 48, . In this figure, only the address lines of the CPU 40 are shown, and the data lines are omitted.

FIG. 2 shows the hardware configuration of the decoder 42. The upper two bits 60 and the next two upper bits 62 of the address signal are input to the CPU 40 from the input port 74.
A recognition signal 68 is input from the input port 76 . Based on this input signal, a selection signal is output from the output port 78 using a table stored in the memory 72.

[0015] Here, the memories are initially 4M, 1M, 1
Suppose that it was set as M, 4M, . At this time, the decoder 42 receives the recognition signal described below, changes the table stored in the memory 72 to the table shown in FIG. 3, and stores the table. Then, based on this changed table, a selection signal is output. In this embodiment, the following recognition signals are used.

[0016] ID bits, which are memory capacity recognition means, are added to the 1M and 4M memory boards in advance. The 1M memory board has a bit 120 added and Vcc applied, as shown in FIG. 4a. The 4M memory board has a bit 122 added and grounded as shown in Figure 4b. Therefore, when a 1M memory board is installed, the recognition signal 68 is sent to the decoder 42.
When a 4M memory board is installed, no recognition signal is generated, so the 4M memory board is recognized as 1M and a 4M memory board is installed.
It is recognized that it is M.

Further, in FIG. 3, the upper bit 60 and the next upper bit 62 of the address signal represent (■■■■), and the 1M memory board represents 44, the 4M memory board represents 46, and the 1M memory board represents 46. Memory boards are shown as 48...

First, when the 1M memory board 44 is installed, the decoder 4 reads from the ID bit 44a as described above.
A recognition signal 68 indicating that it is 1M is sent to 2. When the address is (0000...), the decoder 42 decodes (0000) according to the table in FIG. The decoder 42 then outputs H as the selection signal 66 to the memory board 44. Therefore, when the CPU 10 sends the address (0000...), the memory board 4
4.

Next, a 4M memory board 46 is installed. Similarly, a recognition signal 68 indicating that it is 4M is sent from the ID bit 46a to the decoder 42. When the address is between (0001...) and (0100...), the decoder 42 uses the table in FIG.
(0010), (0011), and (0100) are decoded. The decoder 42 then sends the memory board 46 a
H is output as the selection signal 66. Therefore, CPU10
is the address (0001...), (0010...)
, (0011...), (0100...) are mapped to the memory board 46. The following mapping is done in the same way.

In this way, even if the capacity of the memory board is different from the initial setting, consecutive addresses can be given to each memory board without changing the decoder circuit.

In this embodiment, an ID bit is used as a memory capacity recognition means, but a protrusion is provided on the memory board and the protrusion is sensed by a touch sensor or a photoelectric sensor. For example, 4M
It is also possible to use a memory capacity recognition means that recognizes that .

FIG. 5 shows an overall configuration diagram of a memory control device according to another embodiment. This memory control device is a CPU8
0, register 82, decoder 84, memory board 86,
88, 90, . . The register 82, which is a recognition signal storage means, stores the capacity of the memory board by C.
It is recognized by the PU 80 and sent to the decoder 84. In addition,
Address signals 98, 100, 102 and selection signal 1
04 are connected in the same way as in FIG. In this figure, only the address lines of the CPU 80 are shown, and the data lines are omitted.

First, the installed memory board is 1M.
or 4M is checked as follows. At system startup, register 82 assumes that each installed memory board is a 4M memory board. Then, the CPU 80 sends 4M memory to each memory board.
Send R/W signals for minutes. If the memory capacity is 1M,
The remaining 3M data will be repeatedly written to the 1M address with respect to the 4M address. For example, address (0000...) is set to address (0100...).
), (1000...), (1100...) are repeatedly written. Therefore, address (0
For example, 1 is written to address (000...), and then 2 is written to address (1100...). After that, when the content of the address (0000...) is read, it can be confirmed that if the content is 2, it is 1M, if it is 1, it is 4M, and so on.

[0024] Next, the memory board 86 is configured as described above.
If it is determined that the number is 1M, CPU 80 sends this information to register 82 . register 82 to decoder 8
When this information is sent to 4, the address becomes (0000...
), the decoder 84 uses the predetermined table to
(0000) is decoded. The decoder 84 then outputs H as the selection signal 104 to the memory board 86. Therefore, the CPU 80 has the address (0000...
) is mapped to the memory board 86.

Next, when it is confirmed that the memory board 88 is also 4M, the CPU 80 sends this information to the register 82. When this information is sent from the register 82 to the decoder 84, the address changes from (0001...) to
(0100...), the decoder 84 outputs (0001), (0010), (001...) according to a predetermined table.
1), (0100) is decoded. Then, the decoder 84 sends an H signal to the memory board 88 as a selection signal 104.
Output. Therefore, the CPU 80 uses the address (000
0...) to (0100...) are mapped to the memory board 88. The following mapping is done in the same way.

In this way, consecutive addresses can be given to each memory board without changing the decoder circuit and even if the memory board does not have a hardware memory capacity recognition means.

[0027]

In the memory control device according to the first aspect of the invention, the memory capacity recognition means recognizes the capacity of the attached memory board and outputs the capacity as a recognition signal. The decoder receives the upper bit of the address signal, decodes it, and outputs a selection signal indicating which memory board to select, and the decoding mode is determined by the recognition signal from each memory capacity recognition means. It works by changing it accordingly. Therefore, consecutive addresses can be given to each memory board without changing the decoder circuit.

[0028] In the memory control device according to the second aspect, the memory capacity recognition means recognizes the capacity of the installed memory board;
The capacitance is output as a recognition signal. The recognition signal storage means stores the recognition signal output from the memory capacity recognition means. The decoder receives the upper bit of the address signal, decodes it, and outputs a selection signal indicating which memory board to select, and the decoding mode is determined based on the recognition signal from the recognition signal storage means. Change it accordingly and it will work. Therefore, consecutive addresses can be given to each memory board without changing the decoder circuit and even if the memory board does not have a hardware memory capacity recognition means.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of a memory control device according to an embodiment of the present invention.

FIG. 2 is a hardware configuration diagram of a decoder 42.

FIG. 3 is a diagram showing a table of the decoder 42.

FIG. 4 is a diagram showing ID bits.

FIG. 5 is a configuration diagram of a memory control device according to an embodiment of the present invention.

FIG. 6 is a diagram showing a conventional memory control device.

FIG. 7 is a diagram showing a table of the decoder 12.

[Explanation of symbols]

40... CPU 42... Decoder 44... Memory board 46... Memory board 48... Memory board 60... Upper 2 bits of address signal 62... Next upper 2 bits of address signal 64... Lower bit of address signal 66... Selection signal 68... Recognition signal

Claims (2)

[Claims] 1. A memory control device that controls a plurality of memory boards having different memory capacities, comprising memory capacity recognition means for recognizing the capacity of an installed memory board and outputting the capacity as a recognition signal, and upper bits of an address signal. is received, decodes it, and outputs a selection signal indicating which memory board to select, and operates by changing the manner of the decoding described above according to the recognition signal from each memory capacity recognition means. A memory control device comprising: a decoder that performs a decoder. 2. A memory control device for controlling a plurality of memory boards having different memory capacities, comprising: memory capacity recognition means for recognizing the capacity of an installed memory board and outputting the capacity as a recognition signal; recognition signal storage means for storing a recognition signal to be output; receiving and decoding the upper bits of the address signal; and outputting a selection signal indicating which memory board is to be selected; the decoding mode described above; A memory control device comprising: a decoder that changes and operates according to a recognition signal from a recognition signal storage means.