JPH0772908A - Programmable controller - Google Patents

Abstract

PURPOSE:To prevent the collection of trace data for the display of an on-line trace screen from being affected on the execution of an arithmetic operation. CONSTITUTION:This programmable controller equipped with an instruction pointer 2 which holds an instruction address and a trace buffer 8 which stores the computed result of an instruction, is provided with a first register 10 which holds a trace start instruction address, a second register 9 which holds a trace completion instruction address, a first coincidence detecting means 11 which detects the coincidence of the content of the second register 9 and that of the instruction pointer 2 and first register 10, a second coincidence detecting means 12 which detects the coincidence of the content of the instruction point 2 and that of the register 9, a trace flag holding means 13 set by the register 10 and reset by the register 9, an arithmetic means 6 which executes the instruction of a user program with an address designated by the instruction pointer 2, a trace buffer pointer 7 which designates the address of the buffer 8, and a control means 3 which stores the computed result of the means 6 in the trace buffer with the address designated by the pointer 7.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a programmable controller, and more particularly to a programmable controller for performing trace data collection processing for service processing such as online trace screen display.

[0002]

2. Description of the Related Art A conventional method of trace data collection processing for displaying an online trace screen of a conventional programmable controller is shown in FIG. In FIG. 3, the instruction at the address indicated by the instruction pointer 2 is fetched from the user program 4 into the arithmetic circuit 6 to execute the arithmetic operation. The result is stored in the user data memory 5. Next, the arithmetic unit control circuit 3 increments the instruction pointer 2 and repeats sequential instruction execution. At the same time, the contents of the instruction pointer 2 and the preset trace start address register
The contents of 10 are constantly compared by the coincidence detection circuit 11. When the coincidence detection circuit 11 detects a coincidence, that is, when the execution of the operation reaches the instruction address for starting the trace, the information is transmitted to the operation unit control circuit 3. Based on this information, every time one instruction is executed, a request for trace data collection processing is issued to the trace data collection processor 1 and software is caused to perform processing for storing the calculation result in the trace buffer 8. When the trace data collection process for one instruction is completed,
The trace data collection processor 1 checks whether or not the trace end address has been reached, and if it has not reached, it issues an instruction to the arithmetic unit control circuit 3 to continuously execute the next one instruction. This is repeated until the trace end address is reached. When the trace end address is reached, the trace data collection processor 1 informs the arithmetic unit control circuit 3 that the trace collection processing has been completed, and returns to the normal arithmetic execution operation of the arithmetic unit.

[0003]

As described above, in the conventional programmable controller, when performing the trace data collection processing, as shown in FIG. The processor 1 is requested to perform processing, and the trace data collection processing is performed by software processing. Therefore, there is a problem that the calculation execution time is extended for collecting the trace data.

The present invention has been made in order to solve the above problems, and an object of the present invention is to provide a service process of displaying an online trace screen, and to execute an operation by eliminating the loss time of the trace data collecting process. It is to provide a programmable controller capable of performing.

[0005]

In order to achieve the above object, the present invention stores an instruction pointer for holding an instruction address for executing a user program and an operation result of an instruction in a specific range of the user program. In a programmable controller having a trace buffer, a first register holding an instruction address for starting a trace, a second register holding an instruction address for ending a trace, the instruction pointer and the contents of the first register Match detection means for detecting the match between the instruction pointer and the contents of the second register, and the second match reset means for resetting by the first match detection means. Trace flag holding means to be reset by the coincidence detecting means, and the address designated by the instruction pointer When the trace flag is in the set state, the calculation means for executing the instruction of the user program, the trace buffer pointer for designating the address of the trace buffer, and the calculation result of the calculation means for the address designated by the trace buffer pointer. A control means for storing in the trace buffer is provided.

Further, the arithmetic means comprises a bit arithmetic means for executing a bit instruction and a numerical arithmetic means for executing a numerical instruction. The arithmetic results of the bit arithmetic means are sequentially held and the bit width of the trace buffer is reached. At this time, a shift register for outputting the result of the operation of the bit operation means is provided.

[0007]

In the above arrangement, when the trace flag is set by the first coincidence detecting means when the instruction of the user program at the address designated by the instruction pointer is sequentially executed by the arithmetic means, the control means causes the arithmetic means to operate. The calculation result of is stored in the trace buffer at the address designated by the trace buffer pointer, this operation is performed every time the instruction pointer is updated, and the operation is repeated until the trace flag is reset by the second coincidence detecting means.
This allows the trace data collection process to be performed at the same time as the calculation execution without affecting the calculation execution.

[0008]

FIG. 1 shows the configuration of an embodiment of the present invention. In FIG. 1, the user program memory 4 stores an instruction group in which bit operation instructions and numerical operation instructions are mixed. The instruction pointer 2 holds an instruction address that specifies which instruction in the memory 4 is to be executed. Instruction register 6-1
Holds instructions of the specified user program memory 4. The decoder 6-2 decodes the content latched in the instruction register 6-1 and determines what type of instruction and which operand is used to execute the instruction. The user data memory 5 stores operands and also stores calculation results. The bit operation circuit 6-3 executes a bit operation when the instruction latched in the instruction register 6-1 is a bit operation instruction. The numerical operation circuit 6-4 performs a numerical operation when it is a numerical operation instruction. The trace start address register 10 stores the instruction address for starting the trace. The trace end address register 9 stores the instruction address for ending the trace. The coincidence detection circuit 11 compares the contents of the instruction pointer 2 and the contents of the trace start address register 10 to detect the coincidence state. The match detection circuit 12 has an instruction pointer 2
The contents of the trace end address register 9 are compared with each other to detect the coincidence state. The trace flag F / F13 is set by the coincidence detection circuit 11 and reset by the coincidence detection circuit 12. The trace buffer 8 stores the trace data, and the trace buffer pointer 7 specifies the storage address. The shift register 14 and the shift register control circuit 15 store the bit operation result in the trace buffer 8
In order to store the data efficiently according to the bit width of, the arithmetic unit control circuit 3 controls all of them.

In the above configuration, when executing the user program, the instruction of the user program 4 at the address indicated by the instruction pointer 2 is fetched into the instruction register 6-1. The decoder 6-2 determines whether the fetched instruction is a bit operation instruction or a numerical operation instruction, and what kind of execution form it is. If it is a bit operation instruction, the bit operation circuit 6-3
If it is a numerical operation command, the numerical operation circuit 6-4 performs an arithmetic process. The calculation result is stored in the user data memory 5. Next, the arithmetic unit control circuit 3 increments the instruction pointer 2 and sequentially repeats instruction execution.

On the other hand, simultaneously with the above processing, the contents of the instruction pointer 2 and the preset trace start address register 10 and trace end address register 9 are set.
The contents of are compared by the match detection circuits 11 and 12, respectively,
The trace flag F / F13 is set when the coincidence detection circuit 11 detects a coincidence, that is, when the instruction address for starting the trace is reached. When this flag is set, the arithmetic unit control circuit 3 puts the trace buffer 8 into the write enable state and stores the arithmetic result data in the trace buffer at the address designated by the trace buffer pointer 7. When the instruction fetched in the instruction register 6-1 is a bit operation instruction, the operation result becomes 1 bit, so this is sequentially held in the shift register 14 and buffered until the bit width becomes equal to the bit width of the trace buffer 8. Write to the trace buffer 8. The shift register control circuit 15 controls the shift register 14. As a result, the bit operation result can be efficiently stored in the trace buffer 8. The trace flag F / F13 is reset when the coincidence detection circuit 12 detects a coincidence, that is, when the instruction address for terminating the trace is reached. When this flag is reset, writing of the trace buffer 8 is prohibited and the collection of trace data is completed.

According to the present embodiment, as shown in FIG. 2A, it is possible to collect trace data regardless of the operation execution time, and bit operation instructions and word operation instructions are mixed. Even in the case, the trace data can be efficiently stored.

[0012]

According to the present invention, when an online trace screen is displayed, a programmable controller capable of collecting trace data in a normal state without affecting the execution of calculation by the trace data collecting process is provided. Can be provided.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a programmable controller embodiment of the present invention.

FIG. 2 is a time chart comparing the operation of the present invention and the conventional method.

FIG. 3 is a block diagram of a conventional programmable controller

[Explanation of symbols]

 2 ... Instruction pointer 3 ... Arithmetic unit control circuit 4 ... User program memory 5 ... User data memory 6-1 ... Instruction register 6-2 ... Decoder 6-3 ... Bit arithmetic circuit 6-4 ... Numerical arithmetic circuit 7 ... Trace buffer pointer 8 ... Trace buffer 9 ... Trace end address register 10 ... Trace start address register 11, 12 ... Match detection circuit 13 ... Trace flag F / F

Claims (2)

[Claims] 1. A programmable controller having an instruction pointer for holding an instruction address for executing a user program and a trace buffer for storing an operation result of an instruction in a specific range of the user program, wherein an instruction address for starting a trace is set. A first register for holding, a second register for holding an instruction address for ending the trace, a first match detecting means for detecting a match between the contents of the instruction pointer and the contents of the first register, and the instruction pointer And a second match detecting means for detecting a match between the contents of the second register, a trace flag holding means set by the first match detecting means and reset by the second match detecting means, and the instruction. Arithmetic means for executing the instruction of the user program at the address designated by the pointer; A trace buffer pointer for designating the address of the source buffer, and a control means for storing the calculation result of the calculation means in the trace buffer at the address designated by the trace buffer pointer when the trace flag is set. And programmable controller. 2. The programmable controller according to claim 1, wherein the arithmetic means comprises a bit arithmetic means for executing a bit instruction and a numerical arithmetic means for executing a numerical instruction, and the arithmetic results of the bit arithmetic means are sequentially obtained. A programmable controller provided with a shift register which holds and outputs as a calculation result of a bit calculation means when the bit width of the trace buffer is reached.