JPH06161896A - Semiconductor memory device and address storing system - Google Patents

Abstract

PURPOSE:To provide a high HIT rate regardless of spatial locality provided for a user program concerning a cache memory in a set associative system. CONSTITUTION:This device is provided with an address decoder 5 controlled by a decoder controller 3 and provided with a function for changing a dividing ratio between the TAG part and ENTRY part of an input address, WAY controller 4 for controlling the physical arrangement of a TAG memory 1 and a data memory 2 to the suitable number of WAYs corresponding to a block size at that time, and hit rate detection part 7 for detecting the hit rate for each block size when the cache is turned to an active state, and a control part 8 controls the WAY control circuit 4 and the decoder control circuit 3 so that the block size with the maximum hit rate can be selected and following access can be performed with the memory configuration.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and an address memory system, and more particularly to a cache memory adopting a set associative system in which a cache memory and a main memory are divided into blocks and the blocks are associated with each other. The present invention relates to an address storage system.

[0002]

2. Description of the Related Art A large-capacity main memory using a high-speed memory becomes expensive, and therefore a small-capacity high-speed memory (cache memory) is provided between the CPU and the main memory to achieve fast access. A method of equivalently realizing a large capacity memory is used.

According to this method, the CPU first preferentially accesses the cache memory at the time of executing the program, and if the target data exists (cache hit), the process proceeds as it is, but the cache memory requires it. When no data is found (cache miss hit), the program is interrupted, the contents of the cache memory and the main memory are exchanged, and the program is restarted to access the cache memory.

FIG. 4 is a block diagram of a semiconductor memory device in which a conventional cache memory and a control circuit for controlling the same are integrated on the same semiconductor substrate.
Is a tag (TAG) memory for storing the storage address of the cache data in the cache memory as the data, and 2 is a data memory for storing the cache data, which is composed of a semiconductor memory such as SRAM capable of high speed access. It should be noted that the portion surrounded by the broken line of the data memory 2 or the tag memory 1 in the figure shows one entry out of 256 entries. 7 is an external CPU (not shown)
The address comparator 18 compares the address given by the DMA controller and the address data read from the tag memory 1 with this address to determine whether or not there is a cache hit. A control circuit for controlling input / output of the cache memory 2 and a selector described later according to a control signal or the like, and 19 inputs data from the outside to a way of the cache memory 2 under control of the control circuit 18. It is a selector for switching which WAY data is output to the outside.

Next, the operation will be described. CPU, DM
When the real address of the main memory is given by the A controller or the like, the entry of the TAG memory 1 is selected in the entry address part of the real address (the part surrounded by the broken line of the TAG memory part in the figure). N ways of the selected entry
Contents (TAG address) and T of real address
The address comparator 7 and the AG address portion are simultaneously compared. If there is a match, the address comparator 7 outputs a hit signal to the control unit 18,
The control unit 18 controls the selector 19 according to a timing control signal from the outside so that the contents of the corresponding entry of the data memory 2 can be accessed. If there is no match, the main memory is accessed and at the same time, one of the N ways of the selected entry and the TAG memory 1 are accessed.
And the contents of the data memory 2 are replaced.

By the way, hitherto, it is known that the hit rate of a cache memory is improved in proportion to its capacity. However, increasing the capacity unnecessarily increases the cost and poses a problem. Therefore, the capacity of the cache memory is determined by the balance between performance and cost. Further, it is generally known that there is an optimum block size corresponding to this cache capacity, but this assumes a specific program in which each instruction executed by the CPU is arbitrarily configured at a general ratio. , It was only obtained from the simulated results.

In reality, it is considered that the user can freely program, that the instructions in the program have various configurations, and that the address space is used in various ways within the specified range. That is, the block size of the cache memory uniquely determined by the above-described method is not necessarily optimal depending on the user program, and the capacity of the cache memory may not be fully utilized.

As an example, in order to simplify the description, a set associative cache memory in the case where the number of address bits is 10 bits will be described as an example.
In the set associative method, basically all addresses in the main memory correspond only to the entries in the cache memory determined by the address (entry address) in the block.

FIG. 5 shows the configuration of the TAG memory when the TAG address is 4 bits, the entry address is 4 bits, the incrementer address is 2 bits, and the configuration is 4 WAY. This configuration is effective when the program to be executed has a large temporal and spatial locality. In other words, focusing on the entries, the data accessed immediately before is stored in different entries because the blocks are large. Therefore, even if the data group of consecutive addresses is relatively large, it is possible to hold them all together.

FIG. 6 shows the configuration of the TAG memory when the TAG address is 5 bits, the entry address is 3 bits, the incrementer address is 2 bits, and the configuration is 8 WAY. This configuration is effective when the program to be executed has small temporal and spatial locality. That is, when the number of WAYs is large, focusing on a specific entry means that past data is held for a long time, which is advantageous in that data of many blocks can be stored. The shaded areas in FIG. 5 and FIG. 6 indicate the data to be referred to again, and the numbers indicate the TAG address (block number).

As described above, even if the capacity of the cache memory is the same, the size of the continuous address area that can be held differs depending on the block size and the number of WAYs, and the number of continuous address areas that can be held also differs. . Therefore, when ignoring the user program and determining the configuration of the cache memory, a sufficient hit rate may not be obtained depending on the presence or absence of spatial or temporal localization due to the arrangement of the subroutine and the data group in the user program.

[0012]

The conventional semiconductor memory device is configured as described above, and since the memory configuration is uniquely determined at the chip designing stage, the address division depends on the user program. It was not necessarily optimized, and there was a problem that the hit rate was lowered.

For example, in the configuration having a large block size as shown in FIG. 5, an effect can be expected in a program having a large spatial locality and a region to be repeatedly referred to is relatively large, but a small locality is referred to. Since the number of ways is small in a program with scattered areas, cache misses are repeated and a sufficient hit rate cannot be obtained. On the contrary, the block size is reduced as shown in FIG.
With a configuration having a large number of AYs, a relatively high hit rate can be expected even if the spatial localization of the program is small.

As described above, the conventional cache memory has a problem in that the hit rate depends on the presence or absence of the locality of the user program.

The present invention has been made in order to solve the above problems, and obtains a semiconductor memory device in which the address division of a memory is variable and the memory configuration can be optimally controlled according to a user program. The purpose is to

[0016]

SUMMARY OF THE INVENTION A semiconductor memory device and an address storage system according to the present invention include a bit number changing means for changing the address division of a memory, and a memory configuration sequentially.
A block size changing means for changing several types, a hit rate detecting means for executing a user program with a memory configuration having different block sizes for an arbitrary fixed period to detect a hit rate at that time, and a control means for controlling each of the means. The memory configuration having the high hit ratio is automatically selected and accessed.

[0017]

According to the present invention, the ratio of the number of bits of the TAG address and the entry address and the number of ways can be changed, and the memory configuration is automatically optimized so that the hit rate is improved according to the user program. Therefore, a high hit rate can always be obtained regardless of whether or not the program is localized.

[0018]

【Example】

Example 1. Examples of the present invention will be described below. FIG. 1 is a block configuration diagram including a cache memory which is a semiconductor memory device and a control system thereof according to an embodiment of the present invention. The same reference numerals as those in FIG. 4 denote the same or corresponding portions, and 3 denotes an address decoder 5 described later. The decoder control circuit 4 for controlling W sets the physical arrangement of the TAG memory 1 and the data memory 2 to an appropriate number of ways according to the block size.
AY control circuit, 5 is the TAG part of the input address and ENTR
An address decoder having a function of changing the division ratio of the Y section, 6 is a replacement control circuit for selecting an appropriate WAY when writing new data to the data memory, and 8 is according to the output of a hit rate detection section described later. A control unit 9 for controlling the decoder control circuit 3, the WAY control circuit 4, and the replacement control circuit 6 counts the number of hits within a certain time at the time of access, compares the counter values at each operation and compares the result with the above. It is a hit rate detection unit that outputs to the control unit 8.

Next, the operation will be described with reference to the flowchart of FIG. First, in step S1, the selector 51 forming the address decoder 5 is controlled by the output of the decoder control circuit 3, and the first entry decoder 52 is selected, so that the configurations of the TAG memory 1 and the data memory 2 are predetermined. TAG × EN
The state of “matrix 1” made of TRY is set. Subsequently, in step S2, the hit rate detection unit 9 is initialized and the hit number counter 91 for counting the number of hits is set to zero.

Then, in step S3, caching is started, and the hit number counter 91 counts up each time a hit occurs. In this state, when the fixed time set by the timer 92 has elapsed, the value of the counter 91 is copied to the first hit number storage register 93, and then in step S4 T
The AG memory 1 and the data memory 2 are initialized. next,
The output of the decoder control circuit 3 controls the selector 51 that constitutes the address decoder 5 and, for example, the first and second entry decoders 52 and 53 are both selected, whereby the configurations of the TAG memory 1 and the data memory 2 are configured. TAG × ENT different from the above “Matrix 1”
The "matrix 2" having the RY structure is set (step S5).

Then, in step S6, step S
As in the case of 3, caching is started, the number of hits at that time is counted by the counter 91, and after a certain period of time, the obtained number of counts is transferred to the second hit number storage register 94. Next, in step S7, the values stored in the first hit number storage register 93 and the second HIT number storage register 94 are compared by the comparator 95, and the configuration in which the number of hits is large (TAG × ENTRY) is adopted. In this way, the detection signal is output to the control unit 8.

That is, when it is determined in step S7 that the value of the register 93 is smaller than the value of the register 94,
In step S8, the TAG memory 1 and the data memory 2
The subsequent caching is performed by continuing the state of "matrix 2".

On the other hand, when the value of the register 93 is larger than the value of the register 94, the process proceeds to step S9 to initialize the TAG memory 1 and the data memory 2, and then the step S9.
At 10, the configuration of the TAG memory 1 and the data memory 2 is changed to the state of "matrix 1".

A specific example of the actual memory configuration will be described below. FIG. 3 is a block diagram showing a more detailed structure of the TAG memory 1 and the address decoder 5 of the cache memory. In the figure, 11 is a way selector built in the memories 1 and 2, and an output of the WAY control circuit 4. 8 in response to the WAY configuration / control signal
When WAY is configured, all WAYs from WAY-A to H are
In the WAY configuration, four WAs of WAYs A to D on the entry decoder side activated according to the TAG address A4.
A selector for sending a TAG address to Y. Further, it also has a function of transmitting an enable signal for writing the input TAG address in a predetermined WAY according to the replace way control signal output from the replace control circuit 6.

Here, for simplification of the description, the input address has a 10-bit structure of A0: 9. The address bus is provided with A0: 3 and A4 for the TAG address and A4: 7 and A5: 7 for the entry address. Here, the address A4 is set redundantly because the width of the TAG address is 4 to 5 bits.
The width of the entry address can be changed within 3-4 bi
This is because it can be changed within ts. The number of WAYs can be set to 4 WAY or 8 WAY according to the above address allocation.

In order to configure the above TAG memory, the TA
Considering the case where the G address has a 5 bits configuration of A0: 4, 5 bits are required for each entry. Further, since the number of entries is 8 or 16, the minimum configuration unit of the TAG memory is 8 entries × 5 bits × 4WAY (b
its) and the entry address is A4: 7.
In case of (4 bits width), the number of entries is 2 to the 4th power (=
Since 16 entries are required, the TAG memory 1 is configured by using two TAG memory groups each including the minimum unit. Of these, the tag memory group on the lower side of the page functions as WAY-E to H in the 8-way configuration.

By adopting the above address allocation, the structure of the entry address width is 3 bits, the TAG address width is 5 bits, and 8 WAY, and the entry address width is 4.
Bits and TAG address widths of 4 bits and 4 WAY can be switched to be selectable.

In other words, the entry address selector 51 activates the two entry decoders 52 and 53 in the case of an entry address width of 3 bits and 8 WAY configuration so that both of the two TAG memory groups are accessed and 3b.
The entry address of “its” is the entry decoder 52,
53 is decoded into 8 entries in WAY-A to WAY H, respectively. Entry address width 4bi
Entry decoders 52, 53 for ts, 4 WAY configuration
One of the two is activated to access one TAG memory group, and is decoded by the entry decoder 52 (53) into eight entries in WAYs A to D, respectively.

On the other hand, the ENTRY portion of the address makes the decoded entries of the TAG memory 1 and the data memory 2 (see FIG. 1) accessible via the entry decoder 5.

Further, once the TAG memory writing is performed, the address comparator 7 compares the currently stored TAG address with the newly input TAG address, and if they match, a hit signal is output. The data of the hit WAY is output during the read operation of the CPU, and the hit WAY is output during the write operation of the CPU.
The Y data is rewritten or the TAG address of the same entry is invalidated.

Next, the operation of the address decoder at the time of address division will be described in detail. When the program is highly localized and the address A4 is used as the entry address, that is, when the entry address is 4 bits, the TAG address is 4 bits, and 4 WAY, the entry address selector 51 activates either one of the entry decoders 52 and 53 in the subsequent stage according to the address A4. Turn into.

On the other hand, when the locality of the program is small and the address A4 is used as the TAG address, that is, the entry address 3 bits and the TAG address 5b.
At the time of its, 8 WAY, the address A4 becomes invalid as a TAG address. At this time, the entry address selector 51 activates both the decoders 52 and 53, and sets A5 to A5.
The 3 bits of A7 are transmitted as the entry address.

As described above, the TAG address is always input to all the TAG memories, and the entry decoder 5
2, the TAG address is compared only for the corresponding entry. Address TAG part is A0: 3 4bi
When it is composed of ts, the A4 portion of the TAG memory is not used for comparison and is controlled so as to be ignored when the hit signal is generated.

As described above, according to the present embodiment, the ratio of the number of bits of the TAG address and the entry address is changed by the address decoder 5, and the WAY control circuit 4 performs the TAG.
The number of WAYs of the memory 1 and the data memory 2 is changed, and access is performed for a certain period of time in a configuration including a combination of a plurality of address allocation states and WAY numbers, and the hit rate in each configuration is detected by the hit rate detection unit 9, In response to the detection result of the hit rate detection section 9, the control section 8 selects the matrix state with the highest hit rate by the decoder control circuit 3, WAY.
By controlling the control circuit 4 and the replacement control circuit 6, a high hit rate can always be obtained regardless of the locality of the program.

In the above embodiment, the address allocation is performed by using the entry address 3 bits and the TAG address 5 bits.
s, 8 WAY configuration, entry address 4 bits
Although two combinations of s, TAG address 4 bits, and 4 WAY configuration are obtained, the number of bits configuration at the time of allocation and the number of combinations of allocation are not limited to this, and various changes are possible. Needless to say.

[0036]

As described above, according to the present invention, the block size is automatically optimized according to the spatial locality of each user program without changing the size of the data memory itself, and the cache memory is Since the memory configuration that maximizes the hit rate is selected, the memory can hold more effective data, and the degree of freedom in programming by the user is expanded without lowering the throughput. effective.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration centered on a cache memory of a semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a flowchart for automatically determining an optimum memory configuration for improving the hit rate in the cache memory.

FIG. 3 is a block diagram showing a configuration of a TAG unit of a cache memory for making address allocation variable in the above embodiment.

FIG. 4 is a block diagram showing a configuration centered around a cache memory of a conventional semiconductor memory device.

FIG. 5 is a diagram showing the stored contents of a TAG memory in the case of an 8-block configuration in a conventional semiconductor memory device.

FIG. 6 is a diagram showing stored contents of a TAG memory in the case of a 16-block configuration in a conventional semiconductor memory device.

[Explanation of symbols]

 1 TAG Memory 2 Data Memory 3 Decoder Control Circuit 4 WAY Control Circuit 5 Address Decoder 51 Entry Selector 52 First Entry Decoder 53 Second Entry Decoder 6 Replace Control Circuit 7 Address Comparator 8 Control Section 9 Hit Rate Detection Section 91 Hit Number Counter 92 Timer 93 First Hit Number Storage Register 94 Second Hit Number Storage Register 95 Comparator 11 Way Selector

Claims (2)

[Claims] 1. A semiconductor memory device having a set associative cache memory, in which a cache memory and a main memory are divided into blocks, and the addresses are stored by associating the blocks with each other and the address signal is changed to a TAG address during recording. A bit number changing means for changing the ratio of the number of bits when dividing into entry addresses, a block size changing means for changing the block size of the cache memory, and a cache in which an address having a predetermined bit configuration has a predetermined block size. Controlling means for controlling the bit number changing means and the block size changing means so as to be stored in the memory and setting a mode at the time of storing; and detecting a cache hit rate in each mode set by the controlling means, Hit rate comparing the hit rate in each mode And means out, in accordance with the output of the hit ratio detecting means, a semiconductor memory device, characterized in that the mode setting by the control means is performed so that the hit rate issued 該検 increases. 2. A set associative address storage system in which a cache memory and a main memory are divided into blocks, and addresses are stored in association with each other in the unit, and a TAG address of an address at the time of storage and a bit of an entry address. An address characterized by performing access in a plurality of modes obtained by changing the block ratio of the cache memory while changing the number ratio, and adopting the mode when the hit rate is large in each mode. Memory method.