JP2003131945A - Cache memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a cache memory device with a set associative way to satisfy requirements, which can not be realized by an off the shelf cache memory device with the set associative way, which features a high cache hit ratio but has a problem to consume a large amount of electronic power, but can be realized by reducing power consumption if a low cache hit ratio is acceptable for a processor to execute processes. SOLUTION: A cache memory device embodied by the present invention prepares a mode register and switches a number of cache ways based on register contents. The cache memory device accesses all ways in a set associative mode and decides the way to be used based on a result of hit judgement for each way. The memory device selects the way to be used by using a part of cache addresses in a direct map mode.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a processor equipped with a cache memory.

[0002]

2. Description of the Related Art In recent years, many processors are equipped with a cache memory that can be accessed faster than an external memory in order to improve memory access performance.
The cache memory control methods include a direct map method and a set associative method. The set associative method is a method in which the cache is divided into a plurality of ways and accessed, and a higher hit rate can be realized as compared with the direct map method. However, there is a drawback that power consumption increases because a plurality of ways are accessed simultaneously. In order to solve this problem, Japanese Patent Laid-Open No. 2000-298618 discloses a method of dynamically reducing power consumption during processor operation by providing a mechanism for disabling some sets of a set associative cache. Is listed.

[0003]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
The method of No. 618 reduces cache ways by disabling some sets.
When the number of ways is reduced, the total available cache capacity also decreases. Therefore, there is a problem that the cache hit rate is significantly reduced due to two factors, that is, the decrease in the number of ways and the total available cache capacity.

The present invention solves this problem by providing means for reducing the number of ways used in a set associative cache without reducing the total capacity of the available cache.

[0005]

In the present invention, a mode register is prepared, and the number of ways of the cache is switched according to the contents of the mode register. In the set associative mode, all ways are accessed and the way to be used is determined based on the hit determination result of each way. In direct map mode,
By selecting a way to be used by using a part of the cache access address, it is possible to reduce the number of ways to be used without reducing the total available cache capacity.

[0006]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described with reference to FIGS. In this embodiment, the present invention is applied to a 2-way instruction cache.

FIG. 1 is a block diagram of a processor using the present invention. The processor 9000 includes an instruction cache unit 1, an arithmetic unit 9001, a data cache unit 9002, and a memory control unit 9003. Of these, the instruction cache unit 1, the data cache unit 9002, and the memory control unit 9003 are connected by a processor internal bus 9005. Although not shown in this figure, a peripheral device control unit for controlling peripheral devices connected to the outside of the processor 9000 may be connected to the processor internal bus 9005 to control the peripheral devices from the computing unit 9001. It is possible.

The instruction cache unit 1 is composed of an instruction cache and its control circuit. Calculator 9
Reference numeral 001 denotes arithmetic processing and the data cache unit 90 according to the instruction received from the instruction cache unit 1.
02 is accessed. The data cache unit 9002 is composed of a data cache and its control circuit. The memory control unit 9003 accesses the external memory 9004 according to the memory access request sent via the processor internal bus 9005.

In the processor of this embodiment, the instruction address space is 4 gigabytes, and the address of each instruction is 32.
Specify with byte address of bit width. The instruction cache has a total capacity of 32 kilobytes and is managed in cache line units having a capacity of 16 bytes. Each instruction has a fixed length of 4 bytes, and four instructions can be stored per cache line.

The instruction to be executed is the instruction cache unit 1
If the instruction cache is stored in the instruction cache, that is, if the instruction cache is hit, the arithmetic unit 900
1 reads and executes an instruction from the instruction cache. When a necessary instruction is not stored in the instruction cache, that is, when the instruction cache misses, the necessary instruction is transferred from the external memory 9004 to the instruction cache.
This operation is called cache fill. While the cache fill is being performed, the necessary instruction cannot be supplied to the arithmetic unit 9001, and the arithmetic unit 9001 stops executing the instruction. After this transfer is completed, the arithmetic unit 9001 restarts the execution of the instruction.

The instruction cache unit 1 comprises a cache control circuit 2 and a cache data path 3.

The internal structure of the cache control circuit 2 is shown in FIG. The cache control circuit 2 is a control signal generation circuit 2
3, an address generation circuit 24, a cache control state machine 21, an LRU memory 20, and a mode register 22.

The control signal generation circuit 23 is provided with each memory 30 constituting the cache in the cache data path 3.
control signal 1002 for a, 30b, 31a, 31b
This is a circuit for performing a-d, 1003a-d generation, and the like.

The address generation circuit 24 is a circuit for generating an address 1004 for accessing the cache memory. Address generated here 1004
Is also used as an address for accessing the external memory in the case of a cache miss. The cache control state machine 21 has a state machine inside and controls the cache fill operation at the time of a cache miss.

The LRU memory 20 has a 1-bit width × 1024.
A memory for entries, which stores information indicating which way was last used in the corresponding cache entry. When this cache is operating as a 2-way cache, the contents of the LRU memory 20 are used to determine the way to be overwritten when the cache is filled. LR corresponding to the entry to be cache-filled
If the content of the U memory 20 is 0, the way 0 is the last used way, and the way 1 is the target of overwriting. LR
If the content of the U memory 20 is 1, way 1 is the last used entry, and way 0 is the target of overwriting.

The mode register 22 is a 1-bit register that specifies the cache operation. If the content of the register 22 is 0, the direct map cache mode is set, and if the content of the register 22 is 1, the 2-way cache mode is set. The contents of the mode register 22 are notified to other circuits by the mode signal 1001. The mode register 22 can be changed by an instruction of the processor.

The internal structure of the cache data path 3 is shown in FIG.
Shown in. The cache data path 3 is the tag memory 30.
a, 30b, data memories 31a, 31b, a hit determination circuit 32 for determining a cache hit, and a selector 33 for selecting an instruction read from each way.

Each of the tag memories 30a and 30b has a value of 1.
It is a memory of 9-bit width × 1024 entries, and 18-bit tag address and 1-bit valid bit are stored in each entry. These values are used for hit determination of each way.

Each of the data memories 31a and 31b is a memory of 128-bit width × 1024 entries,
Four instructions are stored in each entry. The capacity of one memory is 16 kilobytes, and by installing two of these, the total capacity of the cache is 32 kilobytes.

The memories 30a, 30b, 31a and 31b have address terminals, data input terminals, data output terminals,
There are a chip select terminal, a write terminal, and a clock terminal. Clocks are not shown in the figure to avoid making the figure complicated. Since the use of the clock is obvious even in a general processor, the description thereof will be omitted even in the following sentences unless otherwise necessary. Memory 30a, 3
The address terminals 0b, 31a, and 31b have bits 13 to 4 of the cache access address 1004.
(Hereinafter, the cache access address 1004 [13:
4]) is connected. The bit position is
The larger number is on the MSB side (upper side). Memory 3
A cache access address 1004 [31:14] and valid bit write data 1007 are connected to the 0 data input terminal. During normal cache fill, the value of the valid bit 1007 to be written is always 1.
When invalidating the cache, the write data 1007 to the valid bit is set to 0.

The operation of the memory is determined by the states of the chip select terminal and the write terminal when the clock rises. This relationship is shown in FIG. When the input signal to the chip select terminal is 0, the memory is not accessed and the power consumption of the memory is almost 0.
When the input signal to the chip select terminal is 1, and the input signal to the write terminal is 1, writing to the memory is performed. If 0, reading from the memory is executed. The signals connected to the respective terminals of each memory are as shown in FIG.

The hit determination circuit 32 makes a cache hit determination using the cache access address 1004, the tag addresses 2200a and 2200b read from the tag memories 30a and 30b, and the valid bits 2201a and 2201b. The hit determination circuit 32 includes two way hit determination circuits 342a and 342b, a flip-flop 341, and an OR circuit 343. The flip-flop 341 is used to match the timing of output data from the memory, which comes out one clock later than the input address.

Way hit determination circuits 342a and 342b
Is the address 21 created by delaying the cache access address 1004 by 1 clock in the flip-flop 341.
00 and the output of the tag memories 30a and 30b, it is a circuit for judging whether or not the way is hit (if the instruction to be executed is already stored in one way, it is said that the way is hit). . The cache mode signal 1001 is input to the way hit determination circuits 342a and 342b, whereby the hit determination method is switched. When one way is hit, the output of the corresponding way hit determination circuit becomes 1. Way 0
Or when the way 1 is hit, the instruction cache is hit. When the instruction cache is hit, the instruction to be executed is the memory 31a or the memory 31b.
Will be stored in. Here, if the hit signal 2400b of the way 1 is 1, that is, the way 1 is hit, it means that the data memory 31b contains an instruction to be executed. Conversely, the hit signal 2400b of way 1 is 0 even though the instruction cache is hit.
That is, if way 1 is not hit, way 0
Will contain the instructions to execute. Therefore, the instruction to be executed can be output to the signal 1200 by controlling the selector 33 with the hit signal 2400b of the way 1. The signal 1200 is connected to the calculator 9001.

When the instruction cache does not hit, the cache hit signal 1005 notifies the cache control state machine 21 of the fact, and the cache control state machine 21 starts the cache fill processing.

Next, FIG. 6 shows the internal structure of the way hit determination circuit 342a. The way hit determination circuit 342b has the same configuration. Output 2500 of comparator 3420
Becomes 1 only when the values of the input 2100 and the input 2200a are all the same, and becomes 0 when 1 bit is not the same. The output 2502 of the comparator 3422 is 1 when the values of the input 2100 and the input 2210a are equal, and is 0 when they are not equal. Output 2503 of OR circuit 3423
Becomes 1 if the input 2502 or the input 1001 is 1, and becomes 0 only when both are 0. The outputs of the way hit determination circuit 342a are signals 2500 and 220.
1a, a way hit only when all the signals 2503 are 1.

Next, the operation in each mode will be described.

First, when the mode signal is 1, that is, 2
The operation in the way cache mode will be described.

In this mode, a 32 kilobyte cache has a capacity of 16 kilobytes per way.
Treated as way cache. When executing a program, it is necessary to read the instruction from the instruction cache. This sequence will be described below. First, the address generation circuit 24 causes the cache access address 10
04 is generated and sent to the cache data path 3.
At this time, the cache access address 1004 [1
4] is also sent to the control signal generation circuit 23.

The control signal generation circuit operates according to the table of FIG. In this table, X indicates Don't care. When performing read access in the 2-way cache mode, the cache access address 1004 [1
4] regardless of the value of 4]
All of a, 1002b, 1002c, and 1002d become 1. As a result, read access is performed to all of the tag memories 30a and 30b and the data memories 31a and 31b. The entry to be read is specified by the cache access address 1004 [13: 4].

Read data 2200a, 2200b, 2201a, 2201b from the tag memories 30a, 30b.
Is sent to the hit determination circuit 32. In this mode, the value of the cache mode signal 1001 is 1, so the OR
The value of the signal 2503 which is the output of the circuit 3423 is always 1. Therefore, the cache access address 1004
Signal 2100 [3:14:31] delayed by 1 clock
1:14] is equal to the tag address 2200a read from the tag memory 30a, and the valid signal 2201a read from the tag memory 30a is 1, it is determined that the way 0 is hit. Similarly, the signal 2100 and the tag address 2200b are equal, and the valid signal 2201
If b is 1, it is determined that way 1 has been hit. If either way 0 or way 1 is hit,
The instruction cache is hit. The hit signal of the way 1 is sent to the selector 33, and if the way 1 is hit, the output 220 of the data memory 31b of the way 1
2b is an arithmetic unit 90 as an output 1200 of the instruction cache
Sent to 01. If the way 1 is not hit, the output 2202a of the data memory 31a of the way 0 is sent to the arithmetic unit 9001 as the output 1200 of the instruction cache. If the instruction cache is hit, the instruction cache output 1200 contains an instruction to be executed by the arithmetic unit 9001, and the arithmetic unit 9001 executes the instruction. When the instruction cache is not hit, the cache hit signal 1005 becomes 0, and the cache control state machine 21 starts the instruction cache fill processing. In this processing, a command read request from the external memory 9004 is issued to the memory control unit 9003 via the processor internal bus 9005. The memory control unit 9003 is an external memory 900
4 is sent to the instruction cache unit 1 via the processor internal bus 9005. In the instruction cache unit 1, the sent instructions are stored in the data memory 3
1a or data memory 31b. Which memory is to be written at this time is determined by the contents of the LRU memory 20 as described in the table of FIG.

Next, when the mode signal is 0, that is, the operation in the direct map cache mode will be described, in this mode, the 32 kilobyte cache is a 1-way cache having a capacity of 32 kilobytes per way, that is, a direct map cache. Treated When executing a program, it is necessary to read the instruction from the instruction cache. This sequence will be described below. First, the address generation circuit 24 generates a cache access address 1004 and sends it to the cache data path 3. At this time, the cache access address 1004 [14] is also sent to the control signal generation circuit 23. The control signal generation circuit operates according to the table of FIG. When performing read access in the direct map cache mode, the cache access address 100
The chip select signal that becomes 1 differs depending on the value of 4 [14]. Below, the cache access address 1004
The operation will be described by taking the case where [14] is 0 as an example. In this case, the chip select signals 1002a and 1002c are 1, but the chip select signals 1002b and 1002d are 0. In this case, read access is performed only to the tag memory 30a and data memory 31a of way 0. Since the tag memory 30b and the data memory 31b are not accessed, power consumption can be suppressed. The entry to be read is the cache access address 10
04 [13: 4].

Read data 22 from the tag memory 30a
00a and 2201b are sent to the hit determination circuit 32.
In this mode, since the value of the cache mode signal 1001 is 0, the value of the signal 2503 becomes equal to the output of the comparator 3422. On the input 2210a of the comparator 3422, the way 0 side (2210a) is set to 0, the way 1 side (2210a).
It is fixed at 1 in b). In this description, since the case where the cache access address 1004 [14] is 0 is considered, the output of the comparator 3422 is 1 on the way 0 side and the output of the comparator 3422 is 0 on the way 1 side. That is, on the way 0 side, the signal 2100 [31:14] obtained by delaying the cache access address 1004 [31:14] by one clock is equal to the tag address 2200a read from the tag memory 30a, and the valid signal read from the tag memory 30a. If 2201a is 1, it is determined that the way 0 is hit. However, since the output 2503 of the comparator 3422 is 0 on the way 1 side, it is determined that the way 1 side does not always hit.
The hit signal of the way 1 is sent to the selector 33, but since its value is 0, the data memory 31 of the way 0 is always present.
The output 2202a of a is sent to the arithmetic unit 9001 as the output 1200 of the instruction cache. If the instruction cache is not hit, the instruction cache fill process is started as in the 2-way cache mode. The instruction read from the external memory 9004 is the data memory 31a.
Alternatively, it is written in the data memory 31b, but here, the cache access address 1004
Since the case where [14] is 0 is considered, it is written in the data memory 31a on the way 0 side according to the table of FIG.

As described above, the cache access address 100
Although the case where 4 [14] is 0 has been described as an example, when the cache access address 1004 [14] is 1, way 1 is used according to the same principle.

With such a configuration, it is possible to dynamically switch between the direct map mode and the 2-way mode by changing the value of the mode register 22 during program execution. The change of the mode register 22 can also be realized by adding a mode register change instruction to the instruction set of the processor 9000 and executing the instruction. Further, by controlling the cache according to the method of this embodiment, it becomes possible to operate the cache correctly when the mode register 22 is changed without initializing the cache.

In this embodiment, the direct map (1
Switching between two ways has been described, but the present invention is not limited to this combination. Various combinations such as direct map and 4-way, 2-way and 4-way can be realized.

Another embodiment of the present invention will be described with reference to FIG. In the present embodiment, the way hit determination circuit 34 for way 1
A selector 350 is added between 2b and the selector 33. The mode signal 1001 is used as a select signal for the selector 350. If the mode signal 1001 is 0, that is, the direct map mode, the cache access address 1004 [14] is delayed by one clock signal 2
100 [14] is output to the signal 2600. If the mode signal 1001 is 1 or 2 way mode, signal 2
The contents of 400b are output on signal 2600.

In the 2-way cache mode, the way 1
Since the selector 33 is switched using the hit determination result 2400b, the path starting from the tag memory 30b may be a severe path in terms of timing. If this path is the worst path in the chip, the operating speed of this path limits the maximum operating frequency of the chip. However, when the mode is set to the direct map mode, the value of the switching signal 2600 of the selector 33 does not depend on the hit determination result 2400b of the way 1,
The operation speed of the path for generating the switching signal 2600 of the selector 33 can be improved as compared with the 2-way mode. In this case, the maximum operating frequency of the chip can be made higher in the direct map mode than in the 2-way cache mode. When the operating frequency of the chip is not changed, the direct map mode can be operated at a lower power supply voltage than the 2-way cache mode.

[0038]

By using the present invention, it is possible to change the number of ways of the cache without changing the total capacity of the cache that can be used during program execution. When the number of ways is reduced, the hit rate of the cache is reduced, but the number of simultaneously accessed memories is reduced, so that power consumption can be reduced. Further, since the total usable cache capacity does not decrease even if the number of ways is reduced, it is possible to suppress a decrease in hit rate.

As described above, by changing the number of ways of the cache during the execution of the program, the trade-off between the processing performance of the program and the power consumption can be made closer to the optimum value.

[Brief description of drawings]

FIG. 1 is an example of a block diagram of a processor using the present invention.

FIG. 2 shows a configuration example of a cache control circuit.

FIG. 3 shows a configuration example of a cache data path.

FIG. 4 is a table showing memory operations.

FIG. 5 is a table showing correspondence of signals connected to each memory.

FIG. 6 is a configuration example of a way hit determination circuit.

FIG. 7 is a table showing a method of generating a control signal for each memory.

FIG. 8 shows another configuration example of the cache data path.

[Explanation of symbols]

1 ... Instruction cache unit, 2 ... Cache control circuit, 3 ... Cache data path, 20 ... LRU memory,
21 ... Cache control state machine, 22 ... Mode register, 23 ... Control signal generation circuit, 24 ... Address generation circuit, 30a ... Tag memory (way 0), 30b ... Tag memory (way 1), 31a ... Data memory (way 0) ), 31b ... Data memory (way 1), 32 ... Hit determination circuit, 33 ... Selector, 341 ... Flip-flop, 342a ... Way hit determination circuit (way 0), 3
42b ... Way hit determination circuit (way 1), 343 ...
OR circuit, 350 ... Selector, 3420 ... Comparator, 34
22 ... Comparator, 3423 ... OR circuit, 3423 ... AND
Circuit, 1001 ... Mode signal, 1002a ... Chip select signal (for tag memory of way 0), 1002b ... Chip select signal (for tag memory of way 1), 100
2c ... Chip select signal (for data memory of way 0), 1002d ... Chip select signal (for data memory of way 1), 1003a ... Write signal (for tag memory of way 0), 1003b ... Write signal (tag of way 1) Memory signal, 1003c ... Write signal (for data memory of way 0), 1003d ... Write signal (way 1)
Data access memory), 1004 ... Cache access address, 1005 ... Cache hit signal, 1007 ...
Valid bit write data, 9000 ... Processor, 9
001 ... arithmetic unit, 9002 ... data cache unit, 9003 ... memory control unit ... 9004, external memory, 9005 ... processor internal bus.

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Kiyokazu Nishioka             1099 Ozenji, Aso-ku, Kawasaki City, Kanagawa Prefecture             Ceremony company Hitachi Systems Development Laboratory F term (reference) 5B005 JJ21 MM01 NN31 TT02 UU41

Claims (13)

[Claims] 1. In a set associative cache composed of a plurality of ways, a way to be accessed is specified by using a part of an access address to the cache in addition to a mode of operating as a normal set associative cache. A cache memory device provided with a mode for performing. 2. In a mode in which a way to be accessed is specified by using a part of an access address to a cache, power consumption is reduced as compared with a case where a memory of a way which is not to be accessed is accessed normally. The cache memory device according to claim 1, wherein the cache memory device is operated. 3. A cache memory device having a storage area for storing information for designating which one of the two modes according to claim 1 is to be used. 4. The cache according to claim 1, wherein in a mode in which a way to be accessed is designated by using a part of an access address to the cache, the number of ways to be designated to be accessed is one. Memory device. 5. The mode according to claim 1, wherein in a mode in which a way to be accessed is specified by using a part of an access address to a cache, the number of ways specified to be accessed is two or more. Cache memory device. 6. In a mode in which a way to be accessed is specified by using a part of an access address to the cache, the operating frequency of the processor can be set higher than that in a mode operating as a normal set associative cache. The cache memory device according to claim 1. 7. The operating voltage of the processor can be set lower in a mode in which a way to be accessed is designated by using a part of an access address to the cache than in a mode operating as a normal set associative cache. The cache memory device according to claim 1. 8. A cache memory device, wherein the two modes according to claim 1 can be dynamically switched during program execution. 9. A cache memory device according to claim 8, wherein it is not necessary to initialize the cache when dynamically switching between the two modes according to claim 1 during program execution. 10. A processor equipped with the cache memory device according to claim 1. 11. A processor comprising instructions for modifying a storage area according to claim 3. 12. A program including a process for changing a storage area according to claim 3. 13. An information processing apparatus equipped with the processor according to claim 10.