JPH05225062A - Disk cache device - Google Patents

Abstract

PURPOSE:To keep a high cache hit rate by dividing blocks in a disk device and a cache memory into sets and mapping them in the same set. CONSTITUTION:Each time read or write is requested to a disk device 4000 within a prescribed time, an access frequency detecting circuit 3400 reads the volume number from an address register 3300 and counts the frequency in access to each logical volume and sends the counted result to a disk cache control circuit. A set address generating circuit 3500 internally has a volume-set correspondence table 3510 and takes a logical volume number 3310 of the disk device 4000 as the input and refers to the volume-set correspondence table 3510 to generate a set address. Normally, respective logical volumes of a cache memory 3200 and those of the disk device 4000 correspond to each other in 1:1, but contents of the volume-set correspondence table 3510 are changed by information of the access frequency detecting circuit 3400.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a disk cache device used in an electronic computer system, and more particularly to a disk cache device adopting a set associative method in mapping.

[0002]

2. Description of the Related Art In order to reduce the processing time for a disk device, a high-speed, small-capacity cache memory is provided between a main memory device and the disk device to store disk data with high reference frequency in the cache memory, In a disk cache device that seeks to shorten the disk access time, one of the requirements for improving its performance is to increase the probability that the accessed data will be found in the cache memory (cache hit rate). The time for determining whether or not the data exists in the cache memory may be shortened, and a method of mapping a part of the data of the disk device to the cache memory well (mapping) becomes important. Conventionally known mapping methods include a full associative method and a set associative method. The full associative method allows a data block (recording unit) of the disk to be mapped to any block of the cache memory. In the set associative method, the disk device is logically divided into several sets, and the blocks of the cache memory are also divided into groups of one row called sets, and mapping is performed in each divided group.

In a disk cache device, generally, when a power failure occurs during operation, there is a risk of data loss in the cache memory. Therefore, at the time of data writing, until data writing to the disk device is completed,
Do not consider the write sequence as finished. Therefore, writing data takes as much time as accessing the disk device.

[0004]

In the conventional mapping method described above, in the full associative method, when determining whether the data to be accessed exists in the cache memory, all blocks of the cache or a very large number of blocks are cached. You need to look at the block. Also, in the set associative system configuration, to determine whether the data to be accessed exists in the cache memory,
It can be done in a shorter time than the full associative method because only a limited number of blocks need to be checked, but on the other hand, once the correspondence between the disk device and the cache memory set is fixed, it is fixed during operation of the computer system.
If access concentrates on a specific logically divided area of the disk device depending on usage conditions, data cannot be stored in the cache memory other than the set corresponding to that area, which is expensive. In addition to not being able to effectively use such a high-speed memory, a small amount of memory for a limited set cannot sufficiently store frequently-referenced data, which may lead to a decrease in the cache hit rate. Also, in the above-described conventional data writing process, the effect of the disk cache device is exerted only when reading data. Therefore, in a system in which the data in the disk device is frequently changed, the data transfer rate has recently been improved. It is also impossible to make full use of the capabilities of the / 0 bus.

The present invention has been made in order to solve such a conventional problem, and determines in a short time whether or not the data to be accessed exists in the cache memory,
Moreover, it is an object of the present invention to provide a high-performance disk cache device that can efficiently use a limited cache memory, maintain a high cache hit rate, and exert a cache effect even when writing data.

[0006]

In order to achieve the above object, the present invention is divided into a plurality of sets as a whole, each of the sets is divided into a plurality of sets, and each of the sets is divided into a plurality of sets. Read / write free and non-volatile cache memory that is divided into blocks, and one or more disk devices that are logically divided into the same number of logical volumes as the set number are provided. Access frequency detecting means for detecting the number of times the upper device requests access per unit time,
Each set of the cache memory is allocated to each logical volume of the disk device in a one-to-one manner, a set address for access is generated, and the correspondence information between the set and the volume is provided. When an extremely biased access to each of the logical volumes is found, the allocation of the cache memory set to the logical volume having the lowest access frequency is stopped, and the set is allocated to the logical volume having the highest access frequency. It is possible to increase the cache memory corresponding to the logical volume, and when the access frequency detecting means detects that the logical volumes are accessed with no extreme bias, the cache memory is set again. Allocating one-to-one logical volumes In the cache memory, a set address generation means that is enabled, a control means that stores a data block given from a higher-level device at a recording position in the cache memory that is designated by the set address generated by the set address generation means, The data is stored in a corresponding recording position in the disk device.

[0007]

According to the present invention, with the above-mentioned configuration, if the access to each logical volume of the disk device is appropriately distributed during the operation of the computer system, the target data is cache memory because of the advantage of the set associative method. It can be determined in a short time whether or not it exists on the upper side, and even when the access to a specific logical volume is concentrated or decreased, the number of sets of cache memory allocated to the logical volume is increased or the cache memory is allocated. It is possible to use cache memory effectively by automatically adjusting it, such as by stopping the allocation of, and without reducing the cache hit rate.

Even when a power failure occurs,
Since the cache memory is non-volatile, it does not lose data and has the function of writing cache data to the disk device, so the data writing process from the host device ends when the writing to the cache memory is completed. Therefore, the access time at the time of writing can be shortened.

[0009]

EXAMPLE An example of the present invention will be described below. In FIG. 2, which shows a computer system to which the present invention is applied, 10
00 is a CPU (upper device), 2000 is a main storage device, 2
Reference numeral 100 denotes an OS operating on the main storage device 2000, 211
0 is a driver that is a program included in the OS 2100, 3000 is a disk cache device, 4000 is a disk device that includes a disk controller, and the inside is logically divided into a plurality of volumes. Manage. Reference numeral 3200 denotes a cache memory for temporarily storing data on the disk device 4000 included in the disk cache device 3000, which is composed of a non-volatile semiconductor memory (eg, EEPROM) that can be freely read / written. There is. Reference numeral 3100 is a directory for storing which data on the disk device 4000 is stored in the cache memory 3200, which is also composed of a nonvolatile semiconductor memory. The disk cache device 3000 does not necessarily have to be an independent device, and can be incorporated in an input / output channel (input / output interface) or a disk control device.

Next, the basic operation will be described. C
When the PU 1000 issues a read request to the disk device 4000 by using the driver 2110, the disk cache device 3000 uses the address of the read request received from the driver 2110 in the directory 31.
00 is checked to see if the data to be accessed exists in the cache memory 3200. If it exists, the data is read from it and the CPU 1000
Transfer to. If the accessed data does not exist in the cache memory 3200, a data block including the data is read from the disk device 4000, this block is stored in an appropriate block of the cache memory 3200, and the directory 3100 is updated. At the same time, the accessed data is transferred to the CPU 1000.

On the contrary, the CPU 1000 is the disk device 400.
When a write request is issued to 0, if the data at the position of the disk device 4000 to be written exists in the cache memory 3200, the data is rewritten. If the data does not exist in the cache memory 3200, the write data is written in the cache memory 32.
00 in an appropriate block, directory 3100
To update.

Since the present invention relates to how and in which part of the cache memory the data block on the disk device is allocated in the above operation, it will be described in detail with reference to FIG. 1 showing the inside of the disk cache device 3000. To do.

In FIG. 1, reference numeral 3300 is a disk device 4.
Address register 340 for storing the address of data designated by a read or write request to 000
0 is an access frequency detection circuit that detects the number of times an access request is made to each logical volume of the disk device 4000 per unit time; 3500 is a set address based on the address of the data to be accessed and the information from the access frequency detection circuit 3400. A set address generation circuit 3600 for generating a disk cache control circuit 3600 for controlling the overall operation of the disk cache device
Is the contents of the directory 3100 and the address register 33
00 is a rewrite processing circuit for performing processing such as replacing a block of the cache memory with a new data block. The cache memory 3200 is connected to the disk device 4000 through the input / output bus 3900. ing.

When the minimum storage unit of the disk device is a sector and a group having a size multiple thereof is a block, an address of data to be accessed is decomposed into a volume number 3310, a block address 3320, and a sector address 3330.

The cache memory 3200 is a memory which can be addressed in sector units, and is decomposed into a set of a plurality of blocks as a whole. If a group of blocks in the same order in each set is taken as a level, a sector in the cache memory is , Set address, level address, and sector address in block.

The directory 3100 is a memory having entries corresponding to blocks in the cache memory 3200, and has a set level array similar to that of the cache memory 3200, and each entry has a cache memory 320.
Disk device 4 stored in the corresponding block of 0
Address of 000 data blocks (volume number,
Block address) is stored.

The access frequency detection circuit 3400 reads the volume number from the address register 3300 each time a read / write operation to the disk device 4000 is requested for a predetermined time, counts the access circuit for each logical volume, and outputs the result to the disk drive. Send to cache control circuit. After the lapse of a predetermined time, each count value is reset once and a new count is started.

The set address generation circuit 3500 has a volume / set correspondence table 3510 therein, and receives the logical volume number 3310 of the disk device 4000 as an input to refer to the volume / set correspondence table 3510 to generate a set address. Normally, the cache memory 3200 and the respective logical volumes of the disk device 4000 are made to correspond one-to-one, but the contents of the volume / set correspondence table 3510 are also changed according to the information of the access frequency detection circuit 3400.

Next, the operation of the embodiment of the present invention will be described with reference to FIGS. When there is a read request from the CPU 1000, the driver 2110 stores the specified data address of the disk device 4000 in the address register 3300. Set address generation circuit 350
0 generates a set address according to the contents of the address register 3300, and one set in the directory 3100 is selected according to the generated set address. The comparison circuit 3700 compares the directory entry contents in the set and the contents in the address register 3300 one by one in order of level. Since this comparison operation is performed only within the selected set, it can be processed in a short time. If the comparison matches at a certain level, the sector to be accessed is stored in the block of the cache memory 3200 corresponding to this entry, its set address is from the set address generation circuit 3500, and the matched level address is the comparison circuit. Are transmitted to the cache memory 3200 and the blocks are designated. Then, the cache memory set in the address register 3300 is allocated, but during the operation of the computer system, the access frequency detection circuit 3400 sets a predetermined time (for example, 1 minute).
The number of accesses to each logical volume in the disk device 4000 is counted and the information is sent to the disk cache control circuit 3600. here,
If the accesses to the logical volume and volume # 0 are concentrated, the number of accesses exceeds a predetermined number, and the difference between the number of accesses to the logical volume and volume # 2 with the least access frequency exceeds the standard, the disk The cache control circuit 3600 activates the rewrite control circuit 3800 to invalidate the data of all blocks of the set (set number 2) of the cache memory corresponding to volume # 2 and the directory entry corresponding to the block. At the same time, the disk cache control circuit 3600
The set address generation circuit 3500 is instructed to change the entry of the volume number corresponding to the set number 2 of the volume / set correspondence table 3510 from 2 to 0.

By the above operation, as shown in FIG. 4, the set of cache memory (set number 2) which has been allocated to volume # 2 is allocated to volume # 0. Therefore, when there is an access request to the volume # 0, the entry of the set of set number 0 is searched first in the directory, and if there is no entry that matches the contents of the address register, then the entry of the set of set number 2 is searched. Will be searched. The reference value of the access circuit to each logical volume per unit time to determine whether there is a bias in accessing the logical volume depends on the number of logical volumes, the capacity of cache memory, the configuration of the calculation system, etc.
The maximum value can be set freely.

When an access request is issued to the volume # 2, since the cache memory is not allocated to the volume # 2, the disk device is directly accessed without searching the directory. During the operation of the computer system, the access to each logical volume is distributed, the access to the volume # 0 is reduced, the access to the volume # 2 is increased, and the detection result of the access frequency detection circuit 3400 is applied to the volumes # 0 and # 2. If the difference in the number of access times per unit time of is within the reference value or the number of access to volume # 0 within the reference value, it is assigned to volume # 0 by the same operation as described above. The set of cache memory (set number 2 or 0) that was previously used is again in volume # 2. Ri attached, a state of FIG.
However, the number of accesses to the volume # 0 per unit time exceeds the reference value, and the difference in the number of accesses to the volume # 0 and the volume # 2 per unit time is within the reference value. Assuming that the difference between the number of accesses to volume # 0 per unit time exceeds the reference value,
The cache memory set that was allocated to volume # 1 by the same operation as described above (set number 1)
Is allocated to the volume # 2 as shown in the figure, and when the difference in the number of accesses per unit time between the volumes # 1 and # 2 and the volume # 0 exceeds the reference value, it is shown in FIG. A set of cache memory is allocated as follows.

As described above, according to this embodiment, the limited cache memory can be used effectively and efficiently by repeating the above-mentioned operations during the operation of the computer system.

Although the above embodiment has been described assuming that one disk having sectors as recording units is connected, the present invention can be applied to disk devices other than the sector system. Not only is it possible to connect multiple units.

[0024]

As is apparent from the embodiments described above, according to the present invention, the set associative method is adopted in which blocks of the disk device and the cache memory are divided into sets and mapping is performed within the same set. , It is easy to judge whether the accessed data block exists in the cache memory in a short time, and the access is concentrated on a specific disk device or a specific area of the disk device during computer system operation. Alternatively, even if the situation becomes unusable due to a decrease or a failure, by automatically adjusting the set of cache memory allocated to the disk device area,
Expensive high-speed memory with limited amount can be effectively used, and the cache hit rate can be maintained without lowering it. Also, by using non-volatile memory for cache memory, it does not disappear even when power failure occurs. Therefore, the reliability is improved, and the write sequence can be ended by writing the data only to the cache memory, so that it is possible to provide the disk cache device which can exert the disk cache effect even at the time of the write command.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration example of a disk cache device according to the present invention.

FIG. 2 is a configuration diagram of a computer system to which the present invention is applied.

FIG. 3 is an operation explanatory schematic diagram illustrating an operation of allocating a set of cache memory to a disk device.

FIG. 4 is an operation explanatory schematic diagram illustrating an operation of allocating a set of cache memory to a disk device.

FIG. 5 is an operation explanatory schematic diagram illustrating an operation of allocating a set of cache memory to a disk device.

FIG. 6 is an operation explanatory schematic diagram illustrating an operation of allocating a set of cache memory to a disk device.

[Explanation of symbols]

 3200 cache memory 4000 disk device 3300 address register 3400 access frequency detection circuit 3500 set address generation circuit 3600 disk cache control circuit 3700 comparison circuit 3800 rewrite processing circuit 3900 input / output bus

Claims (2)

[Claims] 1. A cache memory which is wholly divided into a plurality of sets, each of which is divided into a plurality of blocks, and one disk device which is logically divided into the same number of logical volumes as the number of sets. Alternatively, a plurality of units are provided, and access frequency detection means for detecting the number of times each logical volume is requested to be accessed per unit time, and each set of the cache memory are allocated to each logical volume of the disk device in a one-to-one relationship. When a set address for access is generated, and there is correspondence information between the set and the volume, and there is an extreme bias in the access to each logical volume from the detection result of the access frequency detection means. , Allocation of cache memory set to the least accessed logical volume Can be stopped, the set can be allocated to the logical volume with the highest access frequency, the cache memory corresponding to the logical volume can be increased, and the logical volumes are accessed without any extreme bias. Is detected by the access frequency detecting means, a set address generating means capable of allocating a set of the cache memory and the logical volume one-to-one again, and a set address generated by the set address generating means And a means for controlling to store the data block for which an access request is made in the recording position of the cache memory specified by 1., and a means for writing the data in the cache memory to the corresponding position in the disk device. Disk cache device. 2. The disk cache device according to claim 1, wherein the cache memory is a readable / writable non-volatile memory.