JPH0353320A - Program control system - Google Patents

Abstract

PURPOSE:To form an LSI and at the same time to prevent the rework at occurrence of a bug by using a ROM part and a RAM part to form a decoder which converts a microinstruction into a nanoinstruction. CONSTITUTION:The high order part of a decoder 14 consists of a ROM 14a with the lower order part consisting of a RAM 14b. The nanoinstructions are successively stored in both ROM 14a and RAM 14b from the ROM 14a. Then the decoder 14 receives an access with a 2nd field 12 defined as an address. If a bug occurred in a microprogram is equal to a nanoinstruction corresponding to the ROM 14a, this nanoinstruction is corrected and written into the RAM 14b. While the RAM 14b is corrected if the bug is equal to a nanoinstruction corresponding to the RAM 14b. As a result, an LSI is formed and also the occurrence of a bug can be dealt with.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information processing device controlled by a microprogram, and particularly to a decoder used for horizontal two-level microprogram control.

[Conventional technology]

In the general K, 2-level, Bell microprogram control system,
A microinstruction consists of an array of multiple fields, and this microinstruction is stored in two microinstruction registers. Then, each field of the microinstruction register 20 accesses the decoder, reads nanoinstructions from the decoder, and controls the hardware (HW)' of the information processing device using these nanoinstructions.

When stored, the microinstruction register 20 stores the first, second, third, and fourth fields 21, 22, 23, and 24 (other fields are not shown), etc., as shown in the figure.
The decoder 25 is accessed in field 26 to read out the nanoinstruction pattern.

By the way, conventional decoders of this type are ROM or R
When AM is used, nanoinstruction patterns are written in advance in these ROMs or RAMs.

[Problem to be solved by the invention]

When using ROM'i as a decoder, for example, if there is a bug in the microprogram (if a bug is detected)
, the nano-instruction pattern corresponding to the bug cannot be corrected, and as a result, the ROM has to be recreated.

On the other hand, when a RAM is used as a decoder, it is necessary to write nanoinstruction patterns into the RAM using something other than a microprogram, and hardware for this is required.

Additionally, in the case of RAM, the degree of integration is generally lower than that of ROM (and when implemented in LSI, etc., a large amount of hardware is required. As a result, there is a problem that the capacity of RAM cannot be increased. be.

An object of the present invention is to provide a microprogram control method that is suitable for LSI implementation and that can deal with the occurrence of bugs.

p1 Lower Margin [Means for Solving the Problem] According to the present invention, a storage unit that is used in an information processing device controlled by horizontal microinstructions and stores nanoinstruction patterns that interpret the microinstructions. The storage unit includes a ROM unit and a RAM unit, and the storage unit is accessed in a predetermined field of the microinstruction to read out the nanoinstruction pattern and control is performed using the nanoinstruction pattern. A microprogram control system is obtained which is characterized by the following.

〔Example〕

Next, the present invention will be explained with reference to examples.

Referring to FIG. 1, the microinstruction register 11 contains 1
A horizontal micro-instruction of words is held, and this micro-instruction is divided into a plurality of first fields 11, second fields 12, third seven fields 15, . . . .

As shown in the figure, for example, a decoder 14 is connected to the microinstruction register 11 corresponding to the second field 12. The upper part of the decoder 14 is a ROM 14a
The lower part is composed of a RAM 14b.

These RoM14a and RAM14b have ROM14
Nanoinstructions are stored sequentially starting from a, and the decoder 14 is accessed using the second field 12 as an address.

Here, the first field 11 and the fifth field 15 are each decoded by hardware (for example, another decoder not shown) and output as microcommands, thereby controlling the hardware.

On the other hand, the second field 12 addresses the decoder 14, whereby the corresponding nanoinstruction is read out from the decoder 14 and the hardware is controlled.

By the way, if a bug occurs in the microprogram and it is a nanoinstruction corresponding to the ROM 14a, this nanoinstruction is corrected and written to the RAM 14b. on the other hand,
If it is a nanoinstruction corresponding to RAM 14b, RAM
14b should be modified.

〔Effect of the invention〕

As explained above, in the present invention, the decoder that converts micro-instructions into nano-instructions is composed of a ROM part and a RAM part, so it is suitable for LSI implementation, and if a bug occurs, it can be
Nanoinstructions in the OM part can be modified and written to the RAM part, and the RAM part can be modified, which has the effect of preventing leaks.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention, and FIG. 2 is a diagram showing a conventional example. 10...Microinstruction register, 11-15...Field, 14...Decoder. l...

Claims (1)

[Claims] 1. Used in an information processing device controlled by horizontal micro-instructions, comprising a storage section storing nanoinstruction patterns that interlead the micro-instructions, and the storage section includes a ROM section and a RAM section. . A microprogram control system, characterized in that the storage unit is accessed in a predetermined field of the microinstruction to read out the nanoinstruction pattern, and control is performed using the nanoinstruction pattern.