JPH0196733A - Control memory - Google Patents

Abstract

PURPOSE:To reduce the memory capacity by separating a horizontal microinstruction into a next address, a field which is partly different for each instruction, and a field which overlaps for each instruction and storing them. CONSTITUTION:A memory 31 which receives an access via the output of an address register 20 stores a next address I of a horizontal microinstruction and 1st and 2nd additional addresses. The address I read out of the memory 31 is supplied to the register 20. At the same time, the 1st and 2nd additional addresses are supplied to the memories 32 and 23 respectively. The memory 32 reads out a field II which is partly different for each instruction and supplies the field II to a data register 22. While the memory 23 reads out a field III which overlaps for each instruction and supplies it to a data register 24 in response to the 2nd additional address.

Description

[Detailed Description of the Invention] [Summary] Regarding a control storage device that stores horizontal microprograms, for the purpose of reducing memory capacity, the horizontal microprograms are stored in a control storage device that stores horizontal microprograms. The horizontal microinstructions that make up the
The next address, which is the address of the next instruction, is separated into a field that is partially different for each instruction, and a field that is duplicated for each instruction, and the next address or the next address and the field that is partially different for each instruction are added. and a second layer memory that reads partially different fields for each instruction or partially different fields for each instruction and duplicate fields for each instruction depending on the additional address. Configure.

[Industrial application field]

The present invention relates to a control storage device, and more particularly, to a control storage device that stores horizontal microprograms.

Generally, the sieve system is microprogram controlled. There are two types of microprograms: vertical and horizontal. Horizontal microprograms are used when fast response and conditional branching are required.

The vertical microinstruction that constitutes the vertical microprogram defines all the controls to be executed in a single field of code, and by decoding this code, the type of control is known and the instruction is executed. Further, the address of the next microinstruction to be executed (next address) is not included in the microinstruction.

The horizontal microinstructions that make up the horizontal microprogram define all the controls that should be executed using codes for each of multiple fields (a field is a unit that requires decoding, and the number of bits in each field is smaller than in the vertical type). Each bit in the bit field defines the total control to be performed. Also, the my, ri0 instructions contain the address of the next microinstruction to be executed.

Therefore, the bit width of horizontal microinstructions is larger than that of vertical microinstructions.

[Conventional technology]

FIG. 4 shows a block diagram of an example of a conventional control storage device.

In the figure, an address register 10 stores an address (for example, 12 bits) of a microinstruction to be read next, and a memory 11 is accessed by this address.

For example, 4k (-212) words of horizontal microinstructions with a bit width of 192 bits are stored in the memory 11.
The horizontal microinstruction designated by the above address is read from the memory 11, and each field except the next address is supplied to the data register 12 and stored there. Further, the next address is supplied to the address register 10 and stored therein.

(Problems to be Solved by the Invention) In the conventional device described above, since the pit width of the horizontal microinstruction is as large as 192 pits, the memory 12 is 192 pits wide.
There was a problem in that the 2X4 had a pit and was huge.

The present invention has been made in view of the above points, and an object of the present invention is to provide a control storage device that reduces memory capacity.

[Means for solving problems]

The control storage device of the first invention is a control storage device that stores horizontal microprograms, in which horizontal microinstructions constituting the horizontal microprogram are stored in part with a next address that is the address of the next instruction, and a part of each instruction. A first layer memory (31, 21) for reading out the next address or the next address, a partially different field for each instruction, and an additional address; Read partially different fields in each instruction or partially different fields in each instruction and duplicate fields in each instruction by 2111! It has an i-layer memory (32, 23).

In the control storage device of the second invention, in the control storage device that stores horizontal microprograms, the horizontal microinstructions constituting the horizontal microprogram are stored in part with the next address, which is the address of the next instruction, and each instruction. A first layer memory (33) that separates different fields and fields that overlap in each instruction and reads out the next address and the first additional address, and fields that partially differ in each instruction depending on the first additional address. and a second layer memory (34) from which the second additional address is read, and a third wi layer memory (23) from which the field that overlaps in each instruction is read by the second additional address.

・ [Effect] Horizontal microinstructions have the following characteristics.

■ Each instruction does not use all fields; it uses only a small number of fields.

■ There is a clear distinction between frequently used fields and rarely used fields.

■ Comparing each instruction, only the next 7' address differs, and other fields are often almost the same.

■ When comparing each instruction excluding the next address,
Often only some fields are different and the remaining fields are the same.

From this, the horizontal microinstruction is I Next address π　Some fields are different for each instruction ■ Duplicate fields in each instruction It can be classified into

In the first invention, next address 1. Fields that are partially different for each instruction, and fields that are duplicated for each instruction, are listed in the 11th section.
In the second invention, the first layer memory (21, 31) and the second layer memory (23, 32>) are stored separately.
The memory of the hierarchy (33) and the second floor 11 (1-EIJ (3)
4) and the 319111th memo lJ (23).

By layering in this way, it is possible to reduce the memory capacity required for at least the fields that overlap in each instruction.

(Embodiment) FIG. 1 shows a block diagram of a first embodiment of the control storage control system of the present invention.

In the figure, an address register 20 stores the address (for example, 12 bits) of the next microinstruction to be read, and the memory 21 is accessed by this address.

The memory 21 stores a total of 72 pits, including the next address area of the horizontal microinstruction and a field ■ that is partially different for each instruction, and 11 additional address bits, 4K (-2"
) Word memorization. Of these, the additional address is a field that is duplicated in each horizontal microinstruction.
It is for accessing.

The field (2), which is partially different for each horizontal microinstruction read out from the memory 21 at the specified address, is supplied to the data register 22 and stored therein.

Further, the next address is supplied to the address register 20 and stored therein. The additional address is provided to memory 23.

The memory 23 stores 2K (-211) words of 120 pits of the field ■ which are duplicated in each instruction of horizontal microinstructions according to the value of the additional address, and is specified by the supplied additional address. Field (2) is read out and supplied to the data register 24, where it is stored.

The horizontal micro-instruction stored in the data registers 22 and 23 is executed by decoding the field (2), which is partially different for each instruction, and the field (2), which is duplicated in each instruction, field by field.

In the conventional device, the capacity of the memory 11 is 768 bits (-1
92x4K), whereas in the method of the present invention, the capacity of the memory 21.23 is 572 bits (-83x4 +1).
20x2K), which is a reduction of 196 bits.

FIG. 2 shows a block diagram of a second embodiment of the device of the invention. In the figure, the same parts as in FIG. 1 are designated by the same reference numerals, and their explanations will be omitted.

The memory 31 accessed by the output of the address register 20 is the next address I of the horizontal microinstruction.
and the first and second additional addresses are stored in words 4. The first additional address is for accessing a partially different field (2) for each instruction, and the second additional address is for accessing a duplicate field (2) for each instruction.

The next address read from the memory 31 is supplied to the address register 20, the first additional address is supplied to the memory 32, and the second additional address is supplied to the memory 23.
is supplied to

The memory 32 stores in 3 words a field (■) which is partially different for each horizontal microinstruction according to the Q value of the additional address, and is partially different for each instruction specified by the first additional address supplied. The field ■ is read out and supplied to the data register 22.

In this embodiment as well, the combined capacity of the memories 31, 32, and 23 is significantly reduced compared to the prior art.

FIG. 3 shows a block diagram of a third embodiment of the device of the present invention.

In this figure, the same parts as in FIG. 2 are designated by the same reference numerals, and their explanations will be omitted.

The memory 33 accessed by the output of the address register 20 stores the next address I and the first additional address of each horizontal microinstruction in four words. The first additional address is for accessing a partially different field (2) for each instruction. The next address read from the memory 33 is supplied to the address register 20 and the first additional address is supplied to the memory 34.

The memory 34 stores a field (3) and a second address, which are partially different for each horizontal microinstruction, depending on the value of the additional address. Some fields differ depending on the command■
and the second address and supply the field ■ to the data register 22, and also read the second address to the memory 2.
Supply to 3.

In this embodiment as well, the combined capacity of the memories 33, 34, and 23 is significantly reduced compared to the prior art.

In addition, the more layers there are, the more memory capacity can be reduced. The memory capacity can be smaller than that of the second embodiment.

Note that, if necessary, the additional addresses read from each of the memories 21, 31, and 33 may be set in the address register and then supplied to the subsequent memories 23, 32, and 34, respectively.

〔Effect of the invention〕

As mentioned above, according to the control storage device of the first invention, the memory capacity can be significantly reduced compared to the conventional one, and according to the control storage device of the second invention, the memory capacity can be further reduced compared to the first invention. This is extremely useful in practice.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a first embodiment of the control storage device of the present invention, FIG. 2 is a block diagram of a second embodiment of the device of the present invention, and FIG. 3 is a block diagram of a third embodiment of the device of the present invention. , FIG. 4 is a block diagram of an example of a conventional device. In the figure, 20...Address register, 21.23.31-34...Memory, 22.24-.
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Claims (2)

[Claims] (1) In a control storage device that stores a horizontal microprogram, horizontal microinstructions constituting the horizontal microprogram are stored in a next address that is the address of the next instruction, a field that is partially different for each instruction, and a field that is partially different for each instruction. The next address or the next address and the field that is partially different for each instruction, and
The first layer memory (31, 2
1), and a second layer memory (32
, 23). (2) In a control storage device that stores a horizontal microprogram, the horizontal microinstructions constituting the horizontal microprogram are stored in a next address that is the address of the next instruction, a field that is partially different for each instruction, and a field that is partially different for each instruction. A first layer memory (33) for reading out the next address and a first additional address by separating fields that overlap in each instruction; and fields that partially differ in each instruction depending on the first additional address. and a second layer memory (34) for reading out a second additional address, and a third layer memory (23) for reading fields that are duplicated in each of the instructions using the second additional address. control storage.