JPS62135935A - Microprogram control system microprocessor - Google Patents

Abstract

PURPOSE:To facilitate the change of a microprogram and to define freely the microprogram by storing and executing, from an external memory, the microprogram to the control memory constituted of the rewritable memory. CONSTITUTION:The microprogram prepared by a user is stored to an external memory 101 once and, by a control memory rewriting means 115, written into a rewritable memory part 111a of a control memory 111. The rewritable memory part 111a is accessed by a control memory address 109 stored in a control memory address register 110 as well as a reading exclusive-use memory part 111b. As the result, the read micro-instruction is stored into a micro-instruction register 112 and decoded an executed at a micro-instruction decoder 113.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a microprocessor that performs data processing, and more particularly to a microprocessor that implements its control mechanism using a microprogram control method.

2. Prior Art Regarding microprogram control methods in conventional microprocessors, see, for example, "Microcomputer Architecture," co-authored by Iizuka, Furuya, and Yamaguchi, Oates & Co., Ltd.
In 1980, PP4O-49J was still popular, but regarding the microprogram control system, there are references such as [Microprogramming, written by Hiroshi Hagiwara, Sangyo Tosho, 1978].

FIG. 2 is a block diagram showing the configuration of this conventional microprocessor using the microprogram control system. 201
is an instruction key, 202 is an instruction register, 203 (/i instruction decoder, 204 is a control storage address register, 205
206 is an instruction decoder control circuit; 206 is a control memory; 2o-
rld microinstruction register, 208 is a microinstruction decoder, 209 is 111 for each part of the microprocessor to
The control provided is irises. -Sat 210 marks the boundary between the interior and exterior of the microbe.

The flow of processing that can be carried out by the microprocessor configured as described above and using the microcontroller control method is as follows. The first machine language instruction stored in the external storage 201 is stored in the FugonochisaJyu instruction register 202,
It is decoded by the instruction decoder 203 (-). Command decoder 2
03 generates a control memory address of the control memory 206 in which the microprogram that executes each machine language instruction is stored, and stores it in the control memory address register 204. The micro program configuring the micro program whose start address is the generated control memory address is i.
I;t is sequentially read out from the control memory 206 and stored in the microaddress register 20"T, and is then decoded by the microinstruction decoder 208 to generate various controls for controlling each part in this microprogram. 5,,,-
2 Will be done. In a general microprocessor, the control memory 206
In order to reduce the capacity of microprograms that correspond to different machine language instructions, if the same sequence of microinstructions is included, these sequences of microinstructions (hereinafter referred to as microroutines) are modularized and multiple A method is adopted in which the microprograms share the same information. In this case, the following two methods are often used to share microroutines. The first method is to store the control memory address of the return destination on the stack before starting the shared microroutine, and then store the return destination from the stack after the microroutine is finished, similar to subroutine calls in normal machine language instruction programs. This method extracts the microaddress of the control memory address and continues processing from that control storage address. The second method is to module all microprograms regardless of shared microroutines, and each time an individual microroutine ends, the first control memory address of the next microroutine to be activated is sent to the instruction decoder 2.
This is a method of supplying from 03 onwards. If the 26th method is adopted, the instruction decoder 203 uses the instruction register 2
Different control storage addresses must be generated sequentially for one machine language instruction stored in 02. The instruction decoder 203 is usually made of a logic circuit such as a PLA (programmable logic array), and with the configuration shown above, only one control storage address can be generated for one machine language instruction. Therefore, the instruction decoder 203
By providing a simple sequential circuit for controlling the order of the instructions, it is possible to generate different control storage addresses for one machine language instruction.

This sequential circuit is a second instruction decoder control circuit shown at 205. The output of the instruction decoder control circuit 205 becomes an input to the instruction decoder 203, and when the instruction decoder 203 outputs the start control memory address of the microroutine to be started next, a part of the output is used for instruction decoding. device control circuit 2
It is fed back as an input to 05. By adding the instruction decoder control circuit 205 described above, the p instruction decoder 2
03 is the start control note 7 of the microroutine to be started next
Each time a micro-memory address is generated, a different input condition is given and a different micro-address is generated.

The control memory 206 stores conventional microprograms.
A read-only memory is mainly used in these systems, and some large-scale general-purpose computers can realize dynamic microprogramming by using a rewritable memory for part of the control memory 206. In particular, in a microprocessor using a microprogram control system, the control memory 206 is entirely composed of read-only memory, and the microprogram can be changed by changing the mask pattern of the control memory 206 at the microprocessor manufacturing stage, or by providing memory inside the microprocessor. By accessing this as the control memory 211, the microprogram stored in the external control memory 211 can be replaced, or the external storage medium itself can be replaced to change the microprogram.

Problems to be Solved by the Invention However, in the microprogram control system as described above, the instruction decoder 203 and the instruction decoder control circuit 205 are realized by wired logic, so there is little flexibility in controlling the order of microroutines, and it is difficult to dynamically control the order of microroutines.・There is a problem that it is not suitable for microprogramming.

Among the microprogram modification methods used in conventional microprocessors, the control memory 20 described above is
The method of changing the mask pattern in No. 6 requires a huge amount of time and is not flexible. However, the above-mentioned method of storing a microprogram in an external memory and modifying it is generally slow in accessing the external memory compared to the control memory 206 inside the microprocessor, resulting in degraded processing performance. However, due to the disadvantages of using the external memory and the control memory 206 in the microprocessor, there is a problem that control such as adjustment of access timing becomes complicated due to the difference in access speed.

In view of these points, the present invention provides a dynamic microprogram 9 base that allows flexible microprogram control and easy modification of microprograms.

The purpose of this paper is to provide a microprogram controlled microprocessor with an architecture suitable for mink.

Means for Solving the Problems In order to solve the above-mentioned problems, the present invention provides a first method that takes machine language instructions fetched from external storage and data supplied via an internal data bus as two inputs. selector and
an instruction register that stores the output of the first selector;
a second selector that receives data supplied via the internal data bus and instruction decoder control data as two inputs; an instruction decoder control register that stores an output of the second selector; and the instruction register. and an output of the instruction decoder control register, and outputs a control memory address and the instruction decoder control data, a control memory address register storing the control memory address, and the control memory. A control memory, a part of which stores a microprogram that is read out using the output of an address register as an address, is a rewritable memory, and an external memory for a part or all of the rewritable part of the control memory. This is a microprogram control microprocessor equipped with control memory rewriting means for storing microprograms held in the microprocessor.

According to the above configuration, the present invention allows a user to freely define a microprogram by storing and executing a microprogram from an external memory in a control memory configured with a rewritable memory, and also allows the user to freely define a microprogram in the defined microprogram. Since arbitrary data can be stored in the instruction register and the instruction decoder control register via the internal data bus, it is also possible to dynamically change the activation order of microroutines. Further, since the rewritable control memory is located within the microprocessor, the microprograms in the rewritable control memory and the microprograms in the read-only memory can be used together.

Embodiment FIG. 1 is a block diagram showing the structure of an embodiment of the microprogram control system microprogram of the present invention.

101 is an external storage, 102 is an internal data bus, 103 is a first selector, 104 is an instruction register, 106 is instruction decoder control data, 106 is a second selector, 10 is an instruction decoder control register, 10B is an instruction decoder, 109
Control memory address 110 is a control memory address register, 111 is a control memory, 111a is a rewritable memory part of the control memory 111, 111b is a read-only memory part of the control memory 111b, 112 is a microinstruction register, 113 is a A microinstruction decoder, 114 is a control signal supplied to each part in the microprogram, 115 is a control memory rewriting means, and 116 is a boundary between the inside and outside of the microprocessor.

The operation of the microprogram/control type microprocessor of this embodiment configured as described above will be described below.

1. First, we will explain the operation during execution of the machine language program stored in the external memory 101. The first selector 103 manually inputs the seven items fetched one by one. The first selector 103 selects the machine language instruction: fb, and stores it in the visiting register 104. - The power decoder control register 107 is supplied with a predetermined initial value from the instruction decoder 108 as the instruction decoder control data 105 at the same time as the instructions are stored in the instruction register 104. 2 cell/kuta 106
It is stored via 1~. Metropolitan ordinance decoder *osil5, machine language instructions stored in instruction register 108 and instruction decoder;
15! The initial value stored in the control register 107 is manually inputted into the first control memory address 109 of the microroutine to be activated first among the microprograms necessary for executing the machine language instruction. It generates and stores it in the control storage address register 110, and outputs instruction decoder control data 105 for generating the head storage address of the microroutine to be activated next. The microinstruction of a microroutine starting from the control storage address 110 stored in the control storage address register 110 is read out from the control storage 111 and stored in the microinstruction register 112, and further processed by the microinstruction decoder 113.
A signal 114 is generated which is input to and decoded to control various parts within the microprogram.

When execution of one microinstruction is completed, the control storage address of the next microinstruction to be read is updated according to that microinstruction. The last microinstruction of a microroutine generates a control signal 114 that signals the end of that microroutine. When the control signal 114 is generated, the instruction decoder 108 reads the machine language instruction stored in the instruction register 104 and the data in the instruction decoder control register 107 that has already been updated with the instruction decoder control data 105. The first control memory address 109 of the microroutine to be activated next is generated using the first control memory address 109. When the last microroutine of the microprogram program corresponding to the machine language instruction stored in the instruction register 104 is started, and the last microinstruction of that microroutine is executed, the microprogram is terminated. At the same time, a control signal 114 to inform the user is generated, and the machine language instruction to be executed next is fetched from the external storage 101 and stored in the instruction register 104 via the first selector 103 (7).
A predetermined initial value is stored in the control register 10 as instruction decoder control data 105. Thereafter, by repeating the above processing procedure, the machine language program stored in the external storage 101 is executed.

The processing procedure described below will be explained in detail using a specific example. The instruction decoder 108 is configured with a PLA (programmable logic array), and the data input from the instruction register 104 is input as IR (8 bits), and the data input from the instruction decoder control register 107 as MCTL (4 bits). ), and the output control memory address 109 is set to MA(1
0 bit), 2N instruction decoder control data 105 to NMC
TL (4+Jin.

Furthermore, the flag output for identifying the final microroutine is set to NI (1 bit). A portion of the PLA data of the instruction decoder 108 is shown in FIG. Column 301 is the sequence number of PLA, column 302 is input data I
R, column 303 is input data MCTL, column 304 is output data NMCTL, column 305 is output data MA, column 306
indicates output data NI. 307 is still PLA AND
(logical product) term, 308 indicates ○R (logical sum) term. Third
The AND term °x''' in the figure indicates that the input data is always active whether it is a logic "i" or a logic "○".

Now consider the execution of a machine language instruction whose input data IR is (O○111111). However, input data MCT
It is assumed that the initial value of L is (Qooo). FIG. 4 shows the relationship between input data and output data. Furthermore, output data MA
It is not necessary to use the value as it is as the absolute physical address of the control memory 111; a value that has been further converted or modified may be used as the control memory address 109. In this embodiment, a value obtained by adding 2 bits "O#" to the lower part of the output data MA is used as the control storage address 109. Therefore, the instruction decoder 108 constituted by the PLA having the data shown in FIG. is input data IR=(00111111)
'I B C' (1e
)・(16)・(16) becomes 130'
``1AC'' Start control storage address 109 of three microroutines
generate.

Next, the processing procedure for executing a microprogram created by a user will be explained. The microprogram created by the user is temporarily stored in the external storage 101, and written into the rewritable storage section 111a of the control storage 111 by the side leg storage rewriting means 115. The rewritable storage section 111a of the control memory 111 is a read-only storage section 1.
11b, the microinstruction that is accessed and read by the control storage address 109 stored in the control storage address register 110 is stored in the microinstruction register 112, and decoded and executed by the microinstruction decoder 113. Therefore, by providing a machine language instruction for generating some control memory addresses 109 in the rewritable memory section 111a of the control memory 111, the information stored in the rewritable memory section 111a of the control memory 111 can be stored in the rewritable memory section 111a. microprograms that are currently running can be started. FIG. 6 shows an example of a machine language instruction for executing a microprogram stored in the rewritable storage section 111a of the control storage 111. The machine language instruction of the microprocessor of this embodiment consists of 16 bits, the upper 8 bits 602 of which are input IR to the instruction decoder 108. 3-bit field ENTs of machine language instruction
ol is a field for selecting the top control storage address 109 of the microprogram stored in the rewritable storage section 111a of the control storage 111 to be executed;
ENT, 8 from = (000) to ENT = (111)
A common control storage address 109 can be selected. The read-only memory section 111b of the control memory 111 of the microprocessor of this embodiment has a control memory address 1o9 of OOo'' (
16) to "7FF" (16), and the rewritable storage unit 111a has a control memory address 109 of 64 words from ``ω'' (16) 18 b/ to 83 F'' (1e). Suppose it becomes.

FIG. 6 shows the relevant part of the PLA data of the instruction decoder 108 when the starting control storage address 109 that can be selected in the ENT field 501 is set to 8 consecutive words every 8 words from 800''. The meaning of each column is the same as in Figure 3. Figure 7 shows the relationship between input data and output data.
An example will be shown in which the ENT field 501 is (1o1).

As in the example shown in FIG. 4, if 2 bits "0" are added to the lower part of the output data MA and the value is used as the control storage address 109, then in the example shown in FIG.
8 is the fifth whose ENT field 601 is (101).
For the machine language instruction shown in the figure, two micro-files "828" (16) l (16) called "IBC" are generated for the first control storage address 109 of one chin.

As you can see from this example, 1. The microprogram stored in the rewritable storage section 111a of the control memory 111 uses machine language instructions shown in FIG. Control signal 1 that is started as one microroutine and notifies the end of the microroutine
The microinstruction that generates 14 is executed at a glance. When using another microphone during a microroutine,
Even when branching to Luruno, the microinstruction is executed as soon as it appears. Then, the dummy microroutine (control memory address 109 is "IBC") stored in the readout memory 111b of the control memory 111
The dummy microroutine described above is a microroutine consisting of one word of a microinstruction corresponding to a NOP operation (an instruction that does not perform any operation). and
Its functions will be described later.

Here, a supplementary explanation will be given of a method for storing the microprogram created by the user and stored in the external storage 101 in the rewritable storage section 111a of the control storage 111. In order to avoid confusion in the following description, we will use the following description to describe the ``stored j microprogram.''
16QC required function id, a function to read the first microprogram stored in the external storage 101 and import it into Broselli, the imported first microprogram, 4j4 replacement rl of the entire control memory 111, T
This is a function to write to the function storage section 111a. In the microprocessor of this embodiment, the control memory rewriting means 11 is controlled by the second microprogram stored in the read-only memory section 111b of the control memory 111.
'i'lil controls the functions of 6. FIG. 8 shows machine language instructions for executing the second microprogram. 6th
FIG. 9 shows the relationship between input data and output data for the machine language instruction shown in FIG. 8 in the instruction decoder 10B having the PTA data shown in the figure. Similarly to the above, when 2 bits "0" are added to the lower part of the output data MA and used as the full control storage address 109, the instruction decoder 108
is "424" (16).

Two control storage addresses 1o9 "1 B C" (1e) are generated.

Next, a method of using the microprogram 21-5 created by the user together with a microprogram designed to execute machine language instructions will be described. Normally, microprograms necessary for executing machine language instructions are made resident in the control memory 111, particularly in its read-only memory 111b.

Furthermore, since the microroutines constituting these microprograms need only be activated in a predetermined order, there is no particular problem even if the conventional configuration shown in FIG. 2 is used. However, if an exception occurs in the microprogram, it is not possible to completely change the original starting order of the microroutines. Furthermore, when a part of the control memory 111 is configured as a rewritable memory as in this embodiment, and a microprogram created by a user is stored in the rewritable memory section 111a and executed,
By changing the activation order of subsequent microroutines in a microprogram, it becomes useful to share all microroutines used by other microprograms.

As previously shown in FIG. 7, the microb 2S--20gram stored in the rewritable storage section 111a of the control memory 111 is a microinstruction (if If a branch is made to another microroutine midway through, the microroutine at the branch destination will be executed until a microinstruction that generates a control signal 114 that notifies the end of the entire microroutine appears, but after that, only the dummy microroutine will be fully executed. I'm sorry to have finished processing. This is because even if the program branches to another microroutine, the microroutine to be activated next (in this case, the dummy microroutine) will not change unless the input data to the instruction decoder 108 changes. Therefore, from the microprogram created by the user stored in the rewritable storage section of the control memory 111, it is possible to branch to at most one microroutine and execute all of the microroutines. Therefore, by adopting the configuration shown in FIG. 1, it is possible to change the starting order of microroutines. The first selector 103'f shown in FIG.

Furthermore, by providing the second selector 106, any data can be stored in the instruction decoder control register 107 via the internal data bus 102i. It is possible to store data using instructions.

Therefore, the rewritable storage section 111a of the control storage 111
The end of the microroutine is notified by adding a microinstruction for storing all data to the instruction register 104 and/or instruction decoder control register 107 via the internal data bus 102i to the microprogram stored in the microprogram. When a microinstruction that generates all control signals 114 appears, it becomes possible to activate a microroutine in any activation order of any other machine language instruction, and all microroutines that should be activated after that microroutine are activated. Here, if there is no dummy microroutine and the rewritable memory section 111 of the control memory 111
If the microprogram stored in a is the only microroutine to be started, this microroutine is the final microroutine, and the instruction register 104 and instruction decoder control register 107 among the microroutines. Even if the data stored in the microprogram is changed, the execution of the microprogram ends as soon as the microinstruction that generates the control signal 114 notifying the end of the microroutine appears, and the process shifts to the next machine language instruction. . Therefore, by adding a dummy microroutine, the control signal 11 notifying that this dummy microroutine is the final microroutine is
4.

The processing procedures for each case explained above are summarized in FIG. 10. FIG. 1Q (a) shows the flow of processing when a normal machine language instruction is executed. 1001゜1002.100
3 indicates a microroutine required to execute this machine language instruction. In particular, 1003 indicates the final microroutine. A solid line with a size of 1004 indicates one microinstruction,
The double solid line 10o6 indicates the microinstruction that notifies the end of the microroutine, and the triple solid line 1006 shows the microinstruction that notifies the end of the final microroutine. 1st
From FIG. 10(b) to FIG. 10(e), the microprogram previously stored in the rewritable storage section 111a of the control memory 111 using the machine language instructions shown in FIG. The flow of processing when executed using the machine language instructions shown in is shown below. 10) shows a case where the data stored in the instruction register 104 and the instruction decoder control register 107 are not changed in the microprogram. 1007 is a microprogram (
However, in this case, 10o8 indicates the dummy microroutine (synonymous with microroutine).

10 (0) does not change the data stored in the instruction register 104 and the instruction decoder control register 107 in the microprogram 10o7, as in the case of FIG. The case where the microinstruction is branch microinstruction 26A-/10Q9 and branches to another microroutine 1010 is shown. As explained above, in this case, after microroutine 1010 ends, only dummy microroutine 1008 is executed. FIG. 10(d) shows the instruction register 104 and /-! in the microprogram 1007. , a case where the data stored in the instruction decoder control register 10 is changed using the microinstruction 1Q11 is shown. In this case, when the microinstruction 1012 notifying the end of the microprogram 1007 is executed, another microroutine 1013 is started according to the changed data in the instruction register 104 and /''!! or instruction decoder control register 107. FIG. 10(e) shows the microprogram 1 in the case of FIG. 10(cl).
In the branch microinstruction 1014 from the middle of 007,
This is done when branching to another microroutine 1015. In this case as well, the branch destination microroutine 101
Execution of microinstruction 1016 which signals the end of step 5 changes the data in instruction register 104 and/or instruction decoder control register 107 to 27, - thus the next microroutine is activated.

Finally, as a special case of the case shown in FIG. 10(e), a method for executing a microb "l-gram" whose size is larger than the storage capacity of the replaceable storage section 111a of the control storage 111 will be explained. The method described in 1) allows the target microprogram to be divided into a number of microroutines each having a size smaller than the above-mentioned storage capacity, and while one of the microroutines is being executed, the remaining microprograms are microprograms i, t such that the microroutines of i, t do not need to be stored on the control memory 111;
Applicable only to c. Instead, divide the target microprogram into several microroutines (hereinafter referred to as user routines), and add the above code to the end of all user routines except for the user routine that should be started last. Instruction decoder control register 1
07 to store data (0000) from the internal data bus 102 via the second selector 106, and a microroutine activated at the beginning of the machine language instruction shown in FIG. Then control, -1a fault address 109 starts with "424" (16) /#a
Add -1 the branching microinstruction to the beginning of the run (1-1)
3. At the end of the user routine that should be activated last, add a microinstruction that generates a control signal 114 to notify the end of the microroutine and that it is the final microroutine. ．． ζi−, 1) IJ
The machine language instructions shown in FIG. It is assumed that the microroutine is stored in the replaceable storage section 111a of the control record '1λ1111, and that the microroutine that is activated last is a dummy microroutine.Next, using the machine language Q instruction shown in FIG. The data can be changed from the external memory 101 to the control memory 111 using the Coser routine that should be started first.

Note that this machine language instruction performs only the storage operation described above and ends. Next, the machine language instruction shown in FIG. 5 is used to start the first user routine 297, which has already been stored. After the activated user routine finishes executing the microinstructions that are part of its original processing,
Instruction decoder control register 107 (/i'l: data (o
ooo).The data before storage is shown in Figure 9 (
1111)), the program branches to the beginning of the load routine described above. The load routine stores the user routine to be started next from the external storage 101 into the rewritable storage section 111a of the control memory 111 (at this time, the previously executed user routine is destroyed), and then terminates the microroutine. A microinstruction is executed that generates a control signal 114 to notify. At this time, the data in the instruction register 104 remains the machine language instruction shown in FIG. 5, and the data in the instruction decoder control register 107 is (0000
), the instruction decoder 108 again generates the start control storage address 109 of the user routine, so that the next user routine is activated. Thereafter, the rewritable storage units 111aKS of the users 30, - are sequentially executed in the same manner until the final user routine is activated. In the final user routine, the data stored in the instruction decoder control register 107 must not be changed, so after executing the last micro-instruction, a dummy microroutine is executed to execute the target microprogram. Finish. Note that if the starting control memory address 109 of each user routine is different, the start control memory address 109 stored in the instruction register 104 at the end of the user routine executed immediately before each user routine is ENT field 501 of the machine language instruction shown
A microinstruction may be added to change the value corresponding to .

Effects of the Invention As described above, according to the present invention, a microprogram created by a user can be easily stored and executed within a microprogram, and various types already resident in a microprogram created by a user can be easily stored and executed. The utility of
Microprograms can be used flexibly. Furthermore, by applying these functions, it is possible to execute even a microprogram whose size is larger than the storage capacity of the rewritable control storage section actually mounted on the microprocessor. Therefore, a microprogram controlled microprocessor with a flexible architecture can be realized with a limited amount of control memory.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of a conventional microprogram control microprocessor, and FIG. 3 is a block diagram showing the configuration of an embodiment of the present invention. An explanatory diagram of PLA data showing the contents of the instruction decoder, FIG. 4 is an explanatory diagram of the operation of the instruction decoder of FIG. 3 for a certain machine language instruction, and FIG. Figure 6 is an explanatory diagram of PLA data showing the contents of the instruction decoder, similar to Figure 3, and Figure 7 is an explanatory diagram of machine language instructions for executing the microprogram shown in Figure 5. FIG. 6 is an explanatory diagram of the operation of the instruction decoder, FIG. 8 is an explanatory diagram of machine language instructions for storing a microprogram stored in external storage into the rewritable part of control memory, and FIG. 9 is an explanatory diagram of the operation of the instruction decoder. An explanatory diagram of the operation of the instruction decoder of FIG. 6 for the machine language instruction shown in FIG. 8, and FIGS. 10(a) to 10(e) are flowcharts of the microprogram processing in the embodiment of the present invention. 101...External storage, 102...Internal data bus, 103...First selector, 10
4...Instruction register, 106...2nd
selector, 107...instruction decoder control register, 108...instruction decoder, 110...
Control memory address register, 111... Control memory, 111a... Control memory rewritable storage section, 115... Control memory rewriting means. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
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Claims (4)

[Claims] (1) a first selector that receives machine language instructions fetched from external storage and data supplied via an internal data bus as two inputs; and an instruction register that stores the output of the first selector; a second selector that receives data supplied via the internal data bus and instruction decoder control data as two inputs; an instruction decoder control register that stores an output of the second selector; and the instruction register. and an output of the instruction decoder control register, and outputs a control memory address and the instruction decoder control data, a control memory address register storing the control memory address, and the control memory. 1. A microprogram control type microprocessor comprising a control memory storing a microprogram read out using an output of an address register as an address. (2) A control memory in which a part of the control memory is constituted by a rewritable memory, and a first microprogram held in an external memory is stored in part or all of the rewritable memory section of the control memory. 2. A microprogram controlled microprocessor according to claim 1, further comprising rewriting means. (3) A microprogram-controlled microprocessor according to claim 2, wherein the control memory rewriting means is controlled by a second microprogram stored in the control memory. (4) A third microprogram stored in a rewritable storage section of the control memory supplies data to the instruction decoder control register via an internal data bus, using the first control memory address of the second microprogram. 4. The microprocessor according to claim 3, wherein the second microprogram is activated by outputting the instruction from the instruction decoder.