JPS6158042A - Microprogram control system - Google Patents

Abstract

PURPOSE:To attain the small capacity of a microprogram memory by adopting the cosntitution that a jump instruction is executed by an address stored in a memory acessed by an address section of the jump instruction. CONSTITUTION:When a microinstruction read fronm a microprogram memory (muPM)12 by the address designation of a microprogram sequencer (muSEQ)11 and set to a microinstruction register (muIR)13 is a jump instruction, the jump address section is not fed directly to the muSEQ11 to execute the jump instruction of the microprogram. Through the constitution above, the capacity of the muPAM is saved and the microprogram memory address is expanded easily while utilizisng conventional constitution.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a microprogram type information processing apparatus, and particularly to a microprogram control system characterized by the execution of a jump instruction of a microprogram.

[Technical background of the invention and its problems]

Microgram sequencer (hereinafter referred to as μSEQ)
, microprogram memory (hereinafter referred to as μPM)
, microinstruction ν register (hereinafter referred to as μIR), etc., is read from μPM under the control of μSEQ, and μIR
Conventionally, when the microinstruction set in the jump instruction is a jump instruction, the jump address part indicated in the jump instruction is
By supplying SEQ, a jump address is supplied to μPM, and the instruction to jump to is fetched.

The conventional microprogram control means in this case is shown in Figure 4.
This will be explained with reference to FIG.

In the configuration of FIG. 4, the address of μPM 2 where the microprogram is stored is updated by μ5EQI, which controls the address of the microprogram. μPM 2
The microinstruction (μprocess) read from the microinstruction is set in μIR3 and executed at any time.

Here, when the Noyande instruction is set in μIRJ, the 7177 part indicating the jump destination of the jump instruction is μ5EQI
Execute the υnoyoung instruction by accessing the jump destination μPM2.

In the configuration shown in FIG. 5, in addition to the configuration shown in FIG. A μPA (hereinafter referred to as μPA) 5 is provided, and when this μPA 5 is accessed, it has the function of changing the software instruction processing routine of the microprogram. Then, the output of this μPA 5 and the jump address section when the noyamp instruction is set in μIRJ are input to the selector 5, and the selected address is supplied to μ5EQI to execute each microfagram noyanno.

However, in such conventional microprogram control means, the soyang address 0 address part of the jump instruction requires a bit width sufficient to access all addresses of μPM. (need to set the bit width wide),
This has resulted in the disadvantage that the capacity of μPM increases.

[Purpose of the invention]

The present invention was made in view of the above circumstances, and aims to reduce the bit width of microinstructions to reduce the capacity of microprogram memory, thereby reducing the overall memory capacity of the microprogram control mechanism. The purpose is to provide a microprogram control method that can perform the following tasks.

Another object of the present invention is to provide a microprogram control system that allows easy expansion of microprogram memory addresses without making major changes to the microgumigram control mechanism.

[Summary of the invention]

The present invention provides a jump address table memory separate from the microprogram memory in the microprogram control mechanism, and when executing a no-young instruction of the microprogram, directly inputs the jump destination address of the microprogram into the no-young address part of the jump instruction. The jump instruction is executed by accessing the above-mentioned young address table memory instead of specifying it. This makes it possible to reduce the bit width of the microinstruction, making it possible to reduce the size of the microprogram memory.

[Embodiments of the invention]

The present invention will be described in detail below with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of the present invention.

In FIG. 1, reference numeral 11 indicates a microprogram sequencer (hereinafter referred to as μSI) that controls the address of the microprogram.
(referred to as Q). 12 is a microprogram memory (hereinafter referred to as μPM) that stores microprograms; $
, 9. Consists of ROM or RAM, μSEQ 71
Accessed by K. 13 is a microinstruction renostar (hereinafter referred to as μIR) for setting and executing the microinstruction read out from μPM 12. 14 is a microinstruction renostar (hereinafter referred to as μIR) for setting and executing the microinstruction read out from μPM 12. 14 is for storing the above-mentioned jungle address table memory in which the actual address of the jump instruction of the microprogram is stored. It is a micro program address memory (hereinafter referred to as μPAM), which is composed of p, ROM or RAM, and μlR.
When the microinstruction set to 13 is a gloss/7″ instruction, it is accessed by the address field and μ5EQII
Supply the Jeannot address of the microprogram to execute the jump instruction.

The operation of one embodiment in the configuration shown in FIG. 1 will be described below. If the microinstruction read from μPM 12 and set in μlR13 by addressing the μ5EQII is a jump instruction, the young address part is not directly supplied to μ5EQII, and the jump address part is used to access. Then, by reading the actual jump address from this μP1M14 and supplying it to μ5EQII, the jump instruction of the microprogram is executed.

Next, the differences between the conventional method shown in FIG. 4 and the above-mentioned embodiment regarding the microprogram jump command will be explained.

As a specific example, if the μPM 12 requires an address up to 64, the address part of the jump instruction would require 16 bits in the conventional method described above.

Also, if we assume that jump instructions are used at a rate of about 10% in this 64 microprogram, and that jump instructions to the same address account for 50%, then the address data required as the actual jump destination address is The amount should be 3.2. That is, this is 3.2
It is only necessary to have a jump address table of KX15 bits, and the memory to store this table is
By preparing the μPAMJ4 described above and accessing this μP1M14, a jump address of the microprogram is generated and a jump instruction is executed.
Then, the address part of the jump instruction should be 12 bits (address 4), and it would be sufficient to prepare a μP1M14 with 4K×15 pits.

FIG. 3 shows the operation section 12 based on the conditions of the address section.
1) shows the format of a jump instruction with added pits. 1) is the instruction format for the conventional method shown in FIG. 4, which requires a 28-bit width μPM2. 2) is the instruction format for the above embodiment, and it can be seen that a 24-bit wide μPM 12 is sufficient.

Comparing this capacity, in the conventional method, 6 4 K x 2 8 bits = 1.
792 Kbit - 64 K x 24 bit = 1.536 Kbl in the example method
t, but this is a comparison of μpM (2, 12), and in the present invention, μPAM (14) is added, so adding the capacity, 4KX15bit = 60Kbit 1.536Kbit + 60 Kbit = 1.5
96 Kbit The difference is 196 Kbit.

Next, when a quantitative comparison is made using elements (ROM or RAM) with the following memory capacities, the results are as shown in Table 1.

Table 1 As is clear from the above comparison, according to one embodiment of the present invention, the capacity of the microprogram memory (μPM) can be reduced, and the microprogram address of the jump instruction newly added in the present invention can be reduced. Even when considering the memory (μPAM), the overall memory capacity can be reduced. In other words, it is possible to easily expand the microzologram memory address while making use of the conventional configuration.

Next, another embodiment of the present invention will be described with reference to FIG.

In FIG. 2, 21 is μSEQ (microprogram sequencer), 22 is μPM (microprogram memory), 23 is μIR (microinstruction register), 24
is μPAM (microgram address memory), and both are μS gQ of the embodiment shown in FIG.
l 1゜μPM12. μlR13, μPAM 1
It has the same function as 4. However, μPAM 24 is slightly different from the above embodiment, and has a jump address generation function.
Additionally, addresses of microprograms indicating each execution routine of software instructions are stored.

25 is a software instruction renostar (hereinafter referred to as IR) similar to the components of the conventional example shown in FIG.
The execution time or the next software instruction to be executed is set,
has been recorded. A part of this IR21 accesses the μPAM24 through the selector 26. As mentioned above, this μPAM 24 stores, in addition to the actual address of the jump instruction similar to the embodiment shown in FIG. 1, the address of the microprogram indicating each execution routine of software instructions. and μl when executing a jump instruction.
Either output of R23 is supplied and accessed by selector 26.

In the embodiment shown in FIG. 2, when the microinstruction set in μlR23 is a no-young instruction, the jump address part is not supplied to μSF;Q21 through the selector 26, but the jump address part is supplied to the selector 26.
The jump address is supplied to the μPAM 24 through the µPAM 24 to access the μPAM 24, the actual jump address is read from the μPAM 24, and the read address is supplied to the μ5EQ 21, thereby executing the Noyoung instruction of the microprogram. Also, due to this p,
It is assumed that access to μPAM 24 from I'R, 25 is also performed through selector 26.

If we compare the capacity between the embodiment shown in FIG. 2 and the conventional system shown in FIG.
It will be as shown in Table-2. (However, the capacity of μPAM ?4 accessed from lR25 is 4K x 15 bits.
shall be. ) As is clear from the above explanation, the memory elements of the microprogram control mechanism can be reduced. Furthermore, switching a device adopting the conventional method shown in FIG. 5 to the method of the present invention can be done by changing only the hardware by changing the μPAM 24, and the peripheral circuits and microglodalam instruction format can be changed. Since it can be used as is, it is easy to expand the microprogram memory address.

〔Effect of the invention〕

As detailed above, the microprogram control mechanism of the present invention has a microprogram address memory that is accessed by the jump address part of a jump instruction, and is configured to execute a Gino-Young instruction using a jump address generated from this memory. By doing so, it is possible to reduce the bit width of the microinstruction, thereby reducing the capacity of the microprogram memory, and accordingly, the memory capacity of the entire microprogram control mechanism can be reduced. Furthermore, the microprogram memory address can be easily expanded.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, m 2r
yl is a block diagram showing another embodiment of the present invention, FIG. 3 is a diagram showing a comparison of the bit configuration of the jump instruction between the conventional example and the above embodiment, and FIGS. 4 and 5 are respectively the conventional example. FIG. 2 is a block diagram showing the configuration. 11.21...Microglodarum sequencer (μ5
EQ), 12.22... Micro program memory (μPM), 13.23... Micro instruction renostar (
μIR), 74. ,? 4... Micro program address memory (μPAM), 25... Software instruction register (IR), 26... Selector.

Claims (3)

[Claims] (1) A microprogram control mechanism having a jump address table memory accessed by a jump address part of a jump instruction, and obtaining a jump destination address from the jump address table memory when a jump instruction is executed. Program control method. (2) The microprogram control system according to claim 1, wherein the jump address table memory is constituted by an independent memory. (3) The microprogram control system according to claim 1, wherein the jump address table memory is provided in a memory for storing microprogram addresses indicating each execution routine of software instructions.