JPS6122816B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Scope of Industrial Application] The present invention relates to a microprogram address control device for a microprogram controlled data processing device, in particular for a microprocessor system.

[Conventional technology]

Conventionally, a microprogram-controlled microprocessor system is usually configured as shown in FIG. In other words, basically microprocessor 1
00, microprogram memory 101, main memory 102, and microprocessor 1
The microprogram address control section in 00 is composed of a macroinstruction register 103, a microprogram address register 104, a macroinstruction register 105, and a microprogram address generation circuit 106.

The data placed in the address register 104 is sent to the microprogram memory 101 through the signal 1C, and in response, one microinstruction is sent to the macroinstruction register 101 through the signal line 1b.
03, and each control is performed. On the other hand, when executing a macro instruction, the instruction word read from the main memory 102 is placed in the macro instruction register 105 in the microprocessor 100 via the data bus 1a, the format of this instruction word is decoded, and the The program address generation circuit 106 generates the start address of the microprogram routine for instruction execution, stores this in the address register 104, and thereafter performs microprogram control in the same sequence as described above. be done. In addition, branches included in the microprogram are also handled by the microinstruction register 103 and the address generation circuit 10.
6, also via the address register 104.

[Problem that the invention seeks to solve]

There are the following drawbacks in controlling such microprogram addresses.

(1) Address flexibility Since the address control section of the microprogram is all built into the microprocessor 100,
The theory of address creation is fixed. Therefore,
Only one address can be obtained depending on the instruction word pattern placed in the macro instruction register 105, resulting in a lack of flexibility. That is, it becomes difficult to implement two or more data processing devices with different instruction systems using the same microprocessor.

(2) Pin network Providing pins dedicated to input of microinstructions and pins dedicated to microprogram address output in one microprocessor is an LSI (Large Scaie
This has the disadvantage that it significantly increases the number of pins (integration) and makes it impossible to insert pins for pin connections or other functions.

Regarding microprocessors using microprogram address control, an instruction decoding device that facilitates the design of the entire microprogram is known (Japanese Unexamined Patent Publication No. 54-5639). There is a description that a microaddress is generated by combining data and a signal other than the microinstruction (data from instruction register 1), but this system uses part of the data from the instruction register as the address source. Since the address sources to be combined are limited, there is a lack of flexibility in generating microprogram addresses.

The present invention has been made in view of the prior art described above, and its object is to provide a microprogram address control device that can provide flexibility in generating microprogram addresses.

[Means for solving problems]

In order to solve the above problems, the present invention provides a method for sequentially reading microinstructions for controlling a data processing device from a microprogram memory.
means for creating a microprogram address in response to an output signal from a macroinstruction register in which a microinstruction read from the microprogram memory and a macroinstruction from the main memory are placed; In a microprogram address control device, the microprogram address generating means includes a macro instruction decoding circuit for decoding an instruction format of an output signal from the macro instruction register, and a subroutine return address. a subroutine return address register in which is placed; and an address signal to be input to the microprogram address setting means in response to each output signal of the macroinstruction register/macroinstruction decoding circuit and subroutine return address register. a microprogram address selection circuit that outputs some signals of the microprogram address selection circuit; and a microprogram address selection circuit that outputs the output signals of the microprogram address selection circuit and some data in the addressing field of the microinstruction read from the microprogram memory. The present invention is characterized by comprising means for synthesizing the data signal and inputting the synthesized data signal to the microprogram address setting means as an address signal.

[Effect]

According to the above configuration of the present invention, the microprogram address generation means includes a microprogram address selection circuit, and this microprogram address selection circuit selects between the macro instruction register, the macro instruction decoding circuit, and the subroutine return address register. The microprogram outputs a portion of the address signal in response to each output signal, and the portion of the signal is combined with some data in the addressing field of the microinstruction from the microprogram memory. - Since the address is placed in the address setting means, it is possible to have more flexibility in generating the microprogram address, compared to the conventional method of simply synthesizing only a part of the macro instruction register as an address source.

That is, in the present invention, the address source that can be synthesized includes the macro instruction decoding circuit and the subroutine return address register, and address synthesis is also performed at instruction branches (multiway jumps) and micro subroutine branches (return addresses). Highly flexible microprogram address control is possible by describing part of the instructions. In other words, this flexibility means that the microprogram memory address at the branch is not fixed.

〔Example〕

Next, specific embodiments for carrying out the present invention will be described in detail with reference to the drawings.

FIG. 2 is a schematic diagram of the configuration of a microprocessor system implementing the present invention. This system basically consists of a data bus 1a, a microprocessor 100', and a microprogram memory 10.
1, a main memory 102 and a microprogram address register 104; the microprogram address control section in the microprocessor 100' consists of a microinstruction register 103, a macroinstruction register 105, and a microprogram address generation circuit 106; The difference between this configuration and the conventional example shown in FIG.
6 to form the microprogram address, and the input line from the microprogram memory 101 to the address generation circuit 106 and the output line of the address generation circuit 106. The point is that they use a common signal line. Provides flexibility in address creation by combining addresses,
By using a common signal line, the number of pins can be reduced. According to this configuration, the number is placed in the microinstruction register 103 read from the microprogram memory 101, or directly placed in the address register 104.

On the other hand, the macro instruction read from the main memory 102 is placed in the macro instruction register 105, and the microprogram address generation circuit 106 outputs the decoding result in the form of a microprogram address, which is placed in the address register 104. I will do it. That is, since the address register 104 can store data from the microprogram address generation circuit 106 and the microprogram memory 101, the data is appropriately combined to form one address. be able to.

FIG. 3 is a detailed diagram of the configuration of a microprocessor system implementing the present invention. This microprocessor system consists of two microprocessors 100'a and 100'b, three microprogram memories 101a divided into 8-bit units,
101b and 101c, a microprogram address register 104, and an address output request decoding gate 301. The microinstruction used in this embodiment consists of 24 bits. Below this
The 24-bit digit is indicated using Mi. Microprogram memory 101a, 101b, 101c
Mi0~7, 8~13 and 22 and
Bits 23, 14 to 21 are stored. Also, the microprogram address consists of 12 bits.
Further, the microprogram address control device according to the present invention includes the address register 104, the gate 301, and the microprocessor 100'a, 1
This is a register creation circuit in 00'b, and this creation circuit is shown in FIG. 6 and will be described later.

First, the basic operation of the system shown in FIG. 3 will be explained.

(1) Normal branch When the microinstruction is in the format shown in FIG. 4a (referred to as format a), a normal microprogram branch is executed. In other words, when Mi0 is “1”,
Bits Mi12 to Mi23 become branch address feeds and are stored in microprogram memory 101b.
Mi12, 13 and 22, 23 are input to the microprogram address register 104 via the signal line 3c and 3e, respectively, and the 8 bits of Mi14 to Mi21 of the memory 101c are input to the microprogram address register 104 via the signal line 3d. The value before the change shown in Figure 5a.
It changes to the value "A" shown in Mi12-23. Furthermore, when the most significant bit Mi0 of the 12 bits Mi0 to Mi11 input via the signal line 3a is "1", the microprocessor 100'b outputs a signal "0" to the signal line 3f to program the microprogram. It has the function of setting the register 104 to data load mode (load request). The address "A" placed in the register 104 is supplied to the microprogram memories 101a, b, c by the microprogram address bus 1c, and the corresponding microinstruction is read out, and the control of the system is based on that microinstruction. will be moved to

(2) At the time of special branching The format shown in Figure 4 b (hereinafter referred to as format b)
When a microinstruction is issued, a special microprogram branch is executed. In other words, when all 3 bits of Mi0 to 2 are “0”, 4 bits of Mi12, 13 and 22, 23
The address data 8 from the microprocessor 100'a is transmitted via signal lines 3c and 3e.
The bits (the value of this data is now "B") are sent to the microprogram via the signal line 3d.
It is input to the address register 104, and the contents of this register 104 are as shown in FIG. 5b, 2.
Mi12, 13, 22, 23 (α, β, γ,
δ) and the value "B" output from the microprocessor 100'a.
At this time, the microprocessor 100'b decodes that the upper 3 bits of the 12 bits of input Mi0 to Mi11 are all "0", and sends "0" to the signal line 3f as in the normal branching. ” signal to put the register 104 into data load mode (load request). On the other hand, at this special branch, bits 2 to 2 of the microprogram address register 104 are
Since 8 bits of 9 are output from the microprocessor 100'a, the output of the microprogram memory 101c must be inhibited at this time. Therefore, when the output on the line 3b of the gate 301, which detects in synchronization with the clock signal φ-N that the upper 3 bits of the 8 output bits of the memory 101a are all "0", is "1", the memory 101c output of the microprocessor 100'a is prohibited, and address output of the microprocessor 100'a is permitted (multi-branch request).

Above, except for the two types of branches, the microprocessor'
The signal 3f from b becomes "1", and the microprogram address register 104 functions as a counter that increments the current content K by 1 in synchronization with the clock signal φ-N as shown in FIG. 5 (increment mode). .

Next, according to FIG. 6, the microprocessor 10
Of the 0'a configuration, the microprogram address generation circuit and its peripheral parts will be explained. This configuration includes a 16-bit macro instruction register 105 connected to the data bus 1a, an 8-bit subroutine return address register 601, a macro instruction decoding circuit 600, a microprogram address selection circuit 602, and input buffers 603 and 6.
04, 607, 608, 3-state output buffer 606 and its driver 605.

The contents of the macro instruction register 105 are transferred to the signal line 6a.
is input to the macro instruction decoding circuit 600, and the instruction format is determined by the decoding circuit 600.As shown in FIG. A 5-bit signal corresponding to is output on line 6d.
Assume that for instruction format 4 shown in FIG. 7d, an 8-bit specific pattern (literal pattern) is output on line 6c as address information.
In addition to the signals on lines 6c and 6d, the contents of macroinstruction register 105 are sent via signal line 6a to the contents of subroutine return address register 601 (8
A signal requesting a subroutine return address register generated within microprocessor 100'a is input to address selection circuit 602 via line 6e, respectively.

The address selection circuit 602 responds to a total of six signals on the input lines 6a, 6b, and 6c, including the five types of signals corresponding to the above-mentioned instruction formats on the line 6d and the signal on the line 6e requesting a subroutine return address. The three types of data are rearranged into an 8-bit pattern shown in FIG. 8 and output. That is, when the signal on line 6e is "0", the signal on line 6d is command format 1.
The patterns shown in FIG.
In this case, the pattern shown in FIG. 8f is output. Here, K1 of d is the macro instruction decoding circuit 600
The literal pattern on line 6c obtained from f
R is the contents of subroutine return address register 601 shown on line 6b. This output result is generated by the microprocessor 1 when the signal 3b issued during the execution of the microinstruction of type b in FIG.
It is sent to the outside of 00'a.

FIG. 9 shows waveforms of each part shown in FIG. 3. During normal branching, the signal on line 3f becomes "0",
Output from microprogram memory 101c
Place Mi14~21 on line 3d, and line 3c, 3e with this
Parts Mi12, 13, 22, and 23 of the output of the microprogram memory 101b above are placed in the microprogram address register 104 as an address A, and the result is reflected on the signal line 1c. Address A is then incremented to A+1. At the time of special branching, the signal on line 3b becomes "1" and the microprogram memory 10
1c output is prohibited and the microprocessor 10
Output B from 0'a is placed on signal line 3d, and this and microprogram memory 1 on lines 3c and 3e.
Part of the output of 01b Mi12, 1, 22, 23 (data α, β, γ, δ) is placed in the microprogram address register 104 as address B', and the result is reflected on signal line 1c. .

Finally, a preferred example of use of the microprogram address control device according to the present invention will be explained with reference to FIG. In this example, the microprogram
Since the address register 104 has a 12-bit configuration, the microprogram memory 101 has a maximum of 4K words. A microinstruction is used when taking a special branch.
Two bits Mi12, 13 and Mi22, 23 are placed in the upper and lower parts of the register 104, and the 8 bits in between are placed in the upper and lower parts of the register 104.
Since the address output from the microprocessor 100'a is set in the bit, for example,
If the special branch is a branch to the beginning of a microprogram routine for instruction execution, the first
As shown in Figure 0 a to d, micro instructions Mi12, 13
Branches to one of pages #0 to #3 (in units of 1K words) depending on whether it is (0,0), (0,1), (1,0), or (1,1). I will do it. This shows that even though the 8-bit branch data from the microprocessor 100'a is uniquely determined by the contents of the macro instruction register 105, it has the flexibility to specify the branch area by microprogramming. . this is,
When it is desired to perform different processes using the same macro instruction pattern, data processing devices with different instruction systems can coexist in one microprocessor.

According to one embodiment of the present invention described above, it is possible to create a wide range of branch addresses with a relatively small microprogram instruction branch address.

In addition, since a part of the microinstruction can be added to the address of an instruction branch or subroutine return, the core branch address is small, so a wide range of branch addresses can be created with small hardware, and microprogramming is more flexible. It has a unique effect. Furthermore, by forming the output line of the address generation circuit and the input line from the microprogram memory using a common signal line, the number of pins of the LSI can be reduced.

〔Effect of the invention〕

As described above, according to the configuration of the present invention, the microprogram address generation means includes a microprogram address selection circuit, and this microprogram address selection circuit includes a macroinstruction register, a macroinstruction decoding circuit, and a subroutine. A portion of the address signal is output in response to each output signal of the return address register, and the portion of the signal is combined with a portion of the data in the addressing field of the microinstruction from the microprogram memory. Since the microprogram address is placed in the microprogram address arranging means in a state in which the be able to.

That is, in the present invention, address sources that can be synthesized include the macro instruction decoding circuit and the subroutine return address register, and address synthesis is also performed at instruction branches (multiway jumps) and micro subroutine branches (return addresses). Highly flexible microprogram control is possible by writing part of the microinstructions. In other words, this flexibility means that the microprogram memory address at the branch is not fixed.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a conventional microprogram address control device, FIG. 2 is a schematic diagram of a microprocessor system including the microprogram address control device according to the present invention, and FIG. 3 is a detailed diagram thereof. Figure 4 is a diagram showing the format of a microinstruction that performs a branch, Figure 5 is a diagram showing the contents of a microprogram address register that changes depending on the microprogram address control device of the present invention, and Figure 6 is a diagram showing the format of a microinstruction that performs a branch. Program address creation circuit diagram, Figure 7 is a diagram showing the format of the macro instruction, Figure 8 is a diagram showing the address pattern to be created,
FIG. 9 is a time chart showing the operation of the microprogram address control device according to the present invention;
FIG. 10 is a diagram showing an example of use of the present invention. 100, 100', 100'a, 100'b...
Microprocessor, 101, 101a, 10
1b, 101c...Microprogram memory, 103...Microinstruction register, 104...
...Microprogram address register, 1
05...Macro instruction register, 106...Address creation circuit, 3d...Common signal line.

Claims (1)

[Scope of Claims] 1. In order to sequentially read microinstructions for controlling a data processing device from the microprogram memory, the microinstructions read from the microprogram memory and the macroinstructions from the main memory are stored. A microprogram address control device comprising: means for creating a microprogram address in response to an output signal from a macroinstruction register created by the microprogram; and means for setting the created microprogram address. - The address generation means includes a macro decoding circuit that decodes the instruction format of the output signal from the macro instruction register, a subroutine return address register in which a subroutine return address is stored, and the macro instruction register.
a microprogram address selection circuit for outputting a signal of a portion of the address signal to be input to the microprogram address setting means in response to each output signal of the macro decoding circuit and the subroutine return address register; The output signal of the program address selection circuit and part of the data in the addressing field of the microinstruction read from the microprogram memory are combined, and the combined data signal is used as an address signal to select the microprogram address location. A microprogram address control device characterized by comprising: means for inputting information to a plurality of means.