JPS61101837A - Arithmetic unit - Google Patents

Abstract

PURPOSE:To decrease the number of chips of an arithmetic unit and to improve the general-purpose applications by applying an execution address of a microinstruction built in an integrated circuit chip from the outside of the chip to execute various kinds of arithmetic with free combination of external instructions. CONSTITUTION:Before the arithmetic unit 1 subjected to chip integration starts arithmetic a control circuit 12 switches a selector 11 via a control line 14 to supply and set a signal from a control line 13 to an address memory circuit 6. Further a head address of the address stored in the circuit 6 is fed from the circuit 12, and a microinstruction address and an address memory circuit address are generated on a latch register 20 by using the address read from the circuit 6 by the address converting circuit 8 through signal lines 7-1-7-n and a status signal of a status signal line 6 from the arithmetic unit 1. Then the execution address of an ROM built in the arithmetic unit 1 is applied from the outside of the chip and various kinds of arithmetic are executed by free combination of external instructions to decrease the number of chips of the arithmetic unit 1.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field to which the invention pertains) The present invention relates to an integrated arithmetic unit that receives a microprogram execution address from outside the chip and performs operations using a built-in microprogram.

(Prior Art) In order to make processors more compact and economical, integrated circuits are essential. However, with current semiconductor technology, it is difficult to integrate the entire processor including a control section, an arithmetic section, a memory section, etc. into one chip. Therefore, for example, 1
When considering chip design, it is essential that the arithmetic unit be general-purpose so that it can be used in various fields, and a new problem arises as to how the arithmetic execution function should be divided between on-chip and off-chip parts.

Conventionally, one-chip arithmetic LSIs have built-in a series of microprograms that implement basic arithmetic functions such as addition, subtraction, multiplication, and division, and when a macro instruction given from outside the chip is triggered, a corresponding series of sequences is executed inside the chip. By controlling it, a predetermined calculation function was realized.

However, with this method, for example, trigonometric functions.

When attempting to execute various functional operations such as logarithmic functions, each time the type of operation changes at the beginning of each operation function, mapping is required each time, and the number of processing steps of micro instructions increases. The drawback was that it took a long time.

(Object of the Invention) In order to solve these drawbacks, the present invention provides execution addresses for microinstructions built into an integrated circuit chip from outside the chip, thereby freely combining microinstructions from the outside to execute various types of microinstructions. The purpose of this invention is to provide an arithmetic unit that realizes a general-purpose arithmetic chip that performs arithmetic operations.

(Structure and operation of the invention) The figure is an embodiment diagram showing the functional block structure of the present invention, 1- is a chip-integrated arithmetic unit, 2 is a ROM that stores micro instructions, 3 is an addition, subtraction, An arithmetic circuit that realizes basic functions such as multiplication and shifting; 4 a test matrix circuit that determines the status of the arithmetic unit based on the branch condition of the microinstruction and the operating condition of the arithmetic circuit; 5, the test matrix circuit 4; The status signal of the arithmetic unit is generated and used to determine the next microinstruction address outside the chip. 6 is an address for storing the next address field of the microinstruction to execute various arithmetic functions. Memory circuit, 6-1 is next address field, 7-1 to 7-n are address memory circuits 6
A signal line 8 is used to transfer the next address field read from the address conversion circuit to the address conversion circuit, and a signal line 8 indicates the next microaddress to be executed and the address of the address memory circuit based on the next address field and the status signal 5 from the arithmetic unit 1. 9 is a microinstruction address signal line, 10 is an address memory circuit address signal line, 11 is a selector, 12 is a control circuit that controls the entire circuit, 13 is an address memory circuit 6 at the beginning of execution of various operations. 14 is a control line that controls the selector 11, 15 is a microinstruction control field that controls the arithmetic circuit 3, 16 is a branch condition field that indicates the microinstruction branch condition, and 17 is a control field 15. 18-1 to 18-n are control lines for supplying branch conditions to the test matrix circuit 4.

19-1 to 19-n are signal lines that display the operation results of the arithmetic circuit 3; 20 is a latch register that temporarily stores address information created in the address conversion circuit 8; 21-1;
~21-n are the control lines 18 corresponding to the branch conditions, respectively.
An AND circuit that tests the operation result of the arithmetic circuit 3 using the signals of -1 to 18-n and the signals of signal lines 19-1 to 19-n, and 22 is the output of the AND circuits 21-1 to 21-n. An OR circuit that creates a status signal for an arithmetic unit using -2
3 and 24 are logical sum circuits for creating a microinstruction address and an address of the address memory circuit 6 from the address information from the signals 1iA7-1 to 7-n and the signal on the status signal line 5.

Next, the present invention will be explained in detail.

Prior to the start of the calculation, the control circuit 12 switches the selector 11 through the control line 14 so that the signal from the control line 13 is supplied to the address memory circuit 6.

The control circuit 12 provides the address memory circuit 6 with a predetermined arithmetic function through the control line 13 and the selector 11.
The first address of a series of addresses stored in the address memory circuit 6 in advance is supplied.

In the address conversion circuit 8, the address information from the signal lines 7-1 to 7-n read from the address memory circuit 6 and the status signal from the status signal line 5 of the arithmetic unit 1 are used to convert the microinstruction address and Address memory circuit generates an address.

That is, in the OR circuit 23, the signal lines 5 and 7-1
Further, the outputs of the signal lines 7-2 to 7-n and the OR circuit 23 are logically summed in the OR circuit 24 and temporarily stored in the latch register 20, and the outputs of the signal lines 9 and 7-n are logically summed. The signal is supplied to the arithmetic unit 1 and the address memory circuit 6 via.

Here, for example, first, the information on the signal line 7-1 is set to "0" so that the address information on the signal lines 7-1 to 7-n indicates an even address.
If the signal value of the status signal line 5 is it I HH, it is stored in the address memory circuit 6 as .

The odd address is output from the address conversion circuit 8,
A signal on the status signal line 5 allows the execution address of an instruction to be changed.

In the arithmetic unit 1, the microinstruction is read out from the ROM 2 according to the signal on the microinstruction address signal line 9, and the arithmetic circuit 3 is controlled through the control line 17.
Branch conditions are supplied to the test matrix circuit 4 through g-1 to g-18-n.

After executing a predetermined calculation function, the calculation circuit 3 connects the signal lines 19-1 to 19-1.
19-n to test matrix circuit 4
supply to. In the test matrix circuit 4, the control line 18
The status of the arithmetic unit 1 is determined from the signals of -1 to 18-n and the signals of signal lines 19-1 to 19-n, and is notified to the outside of the chip via the status signal line 5. That is, in the AND circuits 21-1 to 21-n, the control lines 18-1 to 18
The branch condition -0 is tested, and the logical sum is further performed in the logical sum circuit 22 to generate a status signal on the status signal line 5.

On the other hand, the selector 11 is switched to the address memory circuit address signal line 10 side after reading out the next address field 6-1 from the address memory circuit 6, and the address memory circuit address generated in the address conversion circuit 8 is Address memory circuit 6 via signal line 10
The primary instruction address is supplied to signal lines 7-1 to 7-7.
−n.

Using the address read out to the signal lines 7-1 to 7-n and the status signal on the status signal line 5.

Address conversion circuit 8 stores the next microinstruction execution address and address memory circuit address in latch register 20, and supplies them to signal lines 9 and 10, respectively.

In this way, the address memory circuit 6 is configured in advance so that when the microinstructions are sequentially executed and a predetermined sequence is completed, a specific address, for example, address 0, is generated on the signal lines 9 and 10. Also, at address O of ROM 2, “
0'' is stored at address 0 of the address memory circuit 6, and the arithmetic unit continues to execute the invalid instruction when a series of sequences necessary for the arithmetic function are completed.

As explained above, basic microcontrol instructions are prepared in a single-chip arithmetic unit and can be controlled from outside the chip.

By combining these and supplying a series of addresses for execution, the user's desired arithmetic function can be realized. In the explanation for 6+ and above, microinstruction storage inside the arithmetic unit includes:
Although ROM was used, there will be no problem even if it is replaced with PLA.

(Effects) As explained above, according to the present invention, the execution address of the microinstructions built into the chip is supplied from outside the chip, so the user can use the built-in basic microinstructions to perform various operations. It has the advantage that calculation functions can be efficiently realized with a small number of steps.

[Brief explanation of the drawing]

The figure is an embodiment diagram showing a functional block configuration of the present invention. 1...1-chip integrated arithmetic unit, 2...R
OM, 3...Arithmetic circuit, 4...Test matrix circuit, 5...Status signal line, 6...Address memory circuit, 6-1...Next address field,
7-1 to 7-n...Signal line, 8...Address conversion circuit, 9...Micro instruction address signal line, 10.
...Address memory circuit address signal line, 11...Selector, 12...Control circuit, 13, 14, 17.18
-l-18-n-.-Control circuit. 15... Control field, 16... Branch condition field, 19-1 to 19-n... Signal line, 20...
Latch register, 21-1 to 21-n...AND circuit, 22.23.24...OR circuit.

Claims (1)

[Claims] In an integrated arithmetic unit that executes operations under microprogram control, the microinstruction control field and branch condition field are formed within the arithmetic unit integrated on one chip, and the next instruction address field is placed outside the arithmetic unit. 1. An arithmetic unit characterized by having means for transmitting a status signal necessary for determining the next instruction address from the arithmetic unit, and generating an address for the next microinstruction based on the status signal and the next instruction address field outside the arithmetic unit.