JP3524240B2 - Parallel instruction processing unit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel instruction processing device for simultaneously executing a plurality of instructions.

[0002]

2. Description of the Related Art A conventional parallel instruction processing device is provided with a plurality of instruction execution units, supplies one instruction code to all the instruction execution units in common, and simultaneously executes the same instruction in each of the instruction execution units. Device to execute (Single Instruction Multiple
Data stream instruction processing device (hereinafter referred to as SIMD type instruction processing device) and a plurality of instruction execution units, and a plurality of independent instruction codes are simultaneously read from the instruction memory and supplied to the respective instruction execution units. , A device that executes each instruction in each instruction execution unit (Multiple Instruction Mul
tiple Data stream type instruction processing device, hereinafter referred to as MIMD type instruction processing device). FIG. 2 is a configuration block diagram showing an example of a conventional SIMD type instruction processing device. This SIMD
In the type instruction processing device, the instruction memory 1 stores an instruction code. The instruction code stored in the instruction memory 1 is read at each instruction execution cycle time and stored in the instruction register 2. The instruction code stored in the instruction register 2 is stored in all instruction execution units 3 _{1 in the} next instruction execution cycle.
To 3 _n (n; integer of 1 or more). Register file 4 ₁ to 4 _n is disposed in correspondence to each instruction execution unit 3 ₁ each to 3 _n, each of the two read ports and one write against respective instruction execution unit 3 ₁ to 3 _n It is a multi-port register with ports.

FIG. 3 is a diagram showing an instruction format. The instruction code stored in the instruction register 2 is represented by the instruction format shown in FIG. 3, and is composed of operation designation, source 1 designation, source 2 designation, and destination designation. When the source 1 is designated, the source 2 is designated, and the destination is designated, the register file 4 _{1 in} FIG.
Each register number in to 4 _n is specified. The instruction is the contents (ie, data) of the register specified by the source 1 specification.
And the source 2 specification, the operation specified by the operation specification is performed on the contents (that is, the data) of the register specified, and the result is stored in the register specified by the destination specification. Figure 4 shows the conventional MIMD
It is a block diagram which shows an example of a type command processing device. In this MIMD type instruction processing device, the instruction memory 11 stores an instruction code. The instruction code stored in the instruction memory 11 is read at each instruction execution cycle time and stored in the instruction registers 12 _{1 to} 12 _n . Instruction register 2
_The instruction codes stored in _{1 to} 2 _n are output to the instruction execution units 13 _{1 to} 13 _n in the next instruction execution cycle. The register file 14 is a multi-port register having two read ports and one write port for each of the instruction execution units 13 _{1 to} 13 _n .

The instruction codes stored in the instruction registers 12 _{1 to} 12 _n are similar to those in the SIMD type instruction processing device of FIG.
It is represented by the single instruction format shown in FIG.
It is composed of designation of source 1, designation of source 2, and designation of destination. In the source 1 designation, the source 2 designation, and the destination designation, each register number in the register file 14 in FIG. 4 is designated. The contents of the register specified by the source 1 specification (that is,
Data) and the contents of the register designated by the source 2 designation (that is, data), the operation designated by the operation designation is performed, and the result is stored in the register designated by the destination designation. .

[0005]

However, the conventional parallel instruction processing device has the following problems. That is, in the SIMD type instruction processing device, since the same instruction code is executed at the same time, the capacity of the instruction code that constitutes one program is relatively small, and the size of the instruction code read from the instruction memory 1 at a time is also small. The advantage is that the circuit scale of the instruction memory 1 and the instruction register 2 for reading the instruction code can be reduced. However, since performing a plurality of same instruction, the register file 4 ₁ to 4 _n to be operations must be provided in correspondence to each instruction execution unit 3 ₁ to 3 _n, the register file overall circuit scale There is a problem that becomes large. Further, when performing operations on independent operation target data, can take advantage of parallel execution, performs data processing each instruction execution unit 3 ₁ to 3 _n are to cooperate with each other, each of said instruction execution unit 3 _{1 to} 3 _n
If the data dependency occurs between, or when performing shared data at each instruction execution unit 3 ₁ between to 3 _n, the processing between the instruction execution unit 3 ₁ to 3 _n to ensure consistency of data There is a problem that a special circuit (for example, a memory, a switch, etc.) necessary for waiting and processing for data communication is required, and time required for executing these is generated.

On the other hand, in the MIMD type instruction processing device, the register file 14 referred to in the instruction execution is common, and each instruction execution section 13 _{1 to} 13 _n is given a unique instruction to execute these instructions simultaneously. In addition, since the instruction execution units 13 _{1 to} 13 _{n are} independently referred to at the same time and writing of the operation result by instruction execution is guaranteed, the SIMD
In the case of the type instruction processing device, the waiting of the processing and the sharing of the data between the instruction execution units, which is a problem, are easily performed. However, from each instruction register 2 ₁ to 2 _n to each instruction execution unit 13 ₁
Since a unique instruction code is given to each of .about.13 _n , the capacity of the entire instruction code stored in the instruction memory 11 becomes large. Furthermore, for example, when executing a program for performing sequential processing, there is a problem that a complicated and large-scale instruction code corresponding to the number of instruction execution units must be stored in the instruction memory 11.

[0007]

In order to solve the above-mentioned problems, a first invention is a parallel instruction processing device, wherein a single instruction instruction code for instructing a single instruction to execute one instruction by one instruction. Alternatively, an instruction memory for storing a multiple instruction instruction code for instructing multiple instructions to execute a plurality of instructions with one instruction and an instruction code for executing the instruction, and an instruction code for sending and reading an instruction address to the instruction memory A plurality of microinstruction memories that respectively output microinstruction codes based on the instruction code read from the instruction memory, and a single instruction when the instruction code read from the instruction memory is the single instruction. It is determined that the instruction is one instruction, the single instruction corresponding to the instruction code read from the instruction memory is executed, and the single instruction is executed. When the instruction code read from the instruction memory is the multiple instruction, it is determined that the instruction code is the multiple instruction and one of the plurality of micro instruction memories is activated. A first instruction execution unit that executes one of the multiple instructions based on a micro instruction code from one micro instruction memory; and when the instruction code read from the instruction memory is the multiple instruction, the multiple instruction A plurality of second instruction execution units that determine that there is one and execute the multiple instructions based on each microinstruction code from each microinstruction memory;
A multi-instruction execution end detection circuit that is active in a multi-instruction execution end signal when all of the first instruction execution unit and the plurality of second instruction execution units have finished executing the multi-instruction. There is. Further, the program counter is configured to send the next instruction address, which is the current instruction address incremented, to the instruction memory when the single instruction execution end signal or the multiple instruction execution end signal is active.

According to the first aspect of the present invention, since the parallel instruction processing device is configured as described above, a single instruction read from the instruction memory and executed by the first instruction execution unit, and a plurality of micro instructions are executed. One or more unique to the first instruction execution unit and each of the second instruction execution units stored in the instruction memory and simultaneously executed by the first instruction execution unit and the plurality of second instruction execution units Multiple instructions that are expanded and executed in the microinstruction sequence are executed based on the program stored in the instruction memory. In the execution of a single instruction, when the first instruction executing unit finishes executing the single instruction, the single instruction executing end signal is output from the first instruction executing unit and sent to the program counter. The next instruction address is output from the program counter to the instruction memory, and the instruction is executed at the next instruction execution time. In execution of multiple instructions, the length of each unique microinstruction sequence that is simultaneously executed by the first instruction execution unit and each second instruction execution unit is arbitrary, so the first instruction execution unit and the plurality of first instruction execution units When all of the two instruction execution units have finished executing the multiple instruction, the multiple instruction execution end detection circuit outputs a multiple instruction execution end signal and sends it to the program counter. The next instruction address is output from the program counter to the instruction memory, and the instruction is executed at the next instruction execution time. Therefore, in a certain program, for example, parallel processing such as vector calculation or loop execution is executed as multiple instructions, and sequential processing such as control processing based on a control sequence is executed as single instruction. , The processing performance of the program is maximized.

According to a second invention, in the parallel instruction processing device, when the instruction memory, the program counter, a plurality of microinstruction memories of the first invention, and the instruction code read from the instruction memory are the single instruction, A first instruction execution unit that determines that the instruction is a single instruction and executes the single instruction corresponding to the instruction code read from the instruction memory in a predetermined one instruction execution time; A second instruction execution unit, a multiple instruction execution end detection circuit, and when the single instruction instruction code or the multiple instruction execution end signal is active, the next instruction address obtained by incrementing the current instruction address is sent to the instruction memory. And a program counter which is transmitted after the predetermined one instruction execution time has elapsed. According to the second aspect of the present invention, a single instruction read from the instruction memory and executed by the first instruction execution unit and a single instruction stored in the plurality of micro instruction memories and simultaneously executed by the plurality of second instruction execution units. The multiple instructions executed by being expanded into one or a plurality of microinstruction sequences unique to each of the second instruction execution units to be executed are executed based on the program stored in the instruction memory. When executing a single instruction, a single instruction instruction code is output from the instruction register and sent to the program counter. The next instruction address is output from the program counter to the instruction memory, and the instruction is executed at the next instruction execution time.

In the execution of multiple instructions, the length of each peculiar microinstruction sequence that is simultaneously executed by the second instruction execution unit is arbitrary, so that all of the plurality of second instruction execution units execute the multiple instructions. At the end of, the multiple instruction execution end detection circuit outputs a multiple instruction execution end signal, which is sent to the program counter. The next instruction address is output from the program counter to the instruction memory, and the instruction is executed at the next instruction execution time. Therefore, it is possible to separately install a first instruction execution unit that executes only a single instruction and a plurality of second instruction execution units that execute only microinstruction sequences executed when multiple instructions are executed. Then, if the first instruction execution unit is configured to be optimal for single instruction execution and the plurality of second instruction execution units is configured to be appropriate for microinstruction execution,
The circuit scale is reduced as compared with the parallel instruction processing device of the invention. Therefore, the above problem can be solved.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION First Embodiment FIG. 1 is a block diagram showing the configuration of a parallel instruction processing device according to a first embodiment of the present invention. This parallel instruction processor is
It has an instruction memory 21. This instruction memory 21 is
It has a function of storing an instruction code for executing a program and can read out an instruction code of one word in one clock cycle. The output side of the instruction memory 21 is connected to the input side of the instruction register 22. The instruction register 22 has a function of holding the instruction code S21 read from the instruction memory 21 for one instruction execution time. The output side of the instruction register 22 is commonly connected to the respective input sides of the microinstruction memories 23 ₁ to 23 _n , and is also connected to the first input terminal of the selection circuit 24.
The output side of the micro instruction memory 23 ₁ is connected to the second input terminal of the selection circuit 24.

The output terminal of the selection circuit 24 is connected to the instruction code input terminal of the _first instruction execution section 25 _{1 and} the output terminals of the micro instruction memories 23 ₂ to 23 _n are connected to the second instruction execution sections 25 _{2 to} 25 25, respectively. It is connected to each instruction code input terminal of _n . The micro instruction memories 23 ₁ to 23 _n are
And it has a function of storing each microinstruction code S23 ₁ ~S23 _n for the instruction execution unit 25 ₁ to 25 _n. The instruction execution units 25 _{1 to} 25 _n are arithmetic logic units (Arithm).
etic Logic Unit, hereinafter referred to as ALU),
It has a function of executing a single instruction stored in the instruction memory 21 and a micro instruction stored in each of the micro instruction memories 23 ₁ to 23 _n in one instruction execution time. The source 1 data input terminal s1, the source 2 data input terminal s2, and the destination data output terminal ds of the instruction execution units 25 _{1 to} 25 _n are the source 1 data output terminal s1 and the source of the register file 26, respectively. Two data output terminals s2 and each destination data input terminal ds are connected. The register file 26 has a total of 2n read ports and n
And write ports.

Meanwhile, the execution end signal output terminal e ₁ to e _n of the instruction execution unit 25 ₁ to 25 _n are connected to the input terminals of the n-input AND circuit 27 is a multiple instruction execution end detection circuit . AND circuit 27 is a circuit for taking a logical product of each run end signal output terminal e ₁ to e _n. AND
The output terminal of the circuit 27 is connected to the first input terminal of the selection circuit 28. The instruction execution unit 25 ₁ execution end signal output terminal e ₁ is also connected to the second input terminal of the selection circuit 28. The output terminal of the selection circuit 28 is connected to the clock input terminal ck of the program counter 29. Further, the most significant bit (hereinafter referred to as MSB) output terminal of the instruction register 22 is a selection signal input terminal of the selection circuit 24 and each single instruction / instruction execution unit 25 _{1 to} 25 _n.
It is commonly connected to the multiple command input terminal and the selection signal input terminal of the selection circuit 28. The branch destination address output terminal of the instruction execution unit 25 ₁ is connected to the count start value (that is, initial setting value) input terminal of the program counter 29. The program counter 29 has a function of generating an address signal (that is, an instruction address) S29 for the instruction memory 21. This program counter 29
The next instruction address in is the branch destination address D input from the instruction execution unit 25 ₁ when the branch instruction is executed.
If it is not a branch instruction, it becomes the instruction address next to the current instruction address (that is, the current instruction address + 1).
The output terminal of the program counter 29 is the instruction memory 21.
Is connected to the address input terminal A of.

FIG. 5 is a diagram showing the instruction format of the single instruction format 1. The instruction code stored in the instruction register 22 is the single instruction format 1 shown in FIG.
The MSB is “0”, indicating that this instruction is a single instruction. The operation designation designates the operation type (for example, addition, subtraction, multiplication, division, logical product, logical sum, etc.) to be executed by this instruction, and the source 1 designation and the source 2 designation are registers on the register file that stores the operation target data. The number is specified. The destination designation is to designate the register number on the register file that is the storage destination of the operation result data.

FIG. 6 is a diagram showing the instruction format of the single instruction format 2. This instruction format is a single instruction format for branching, the MSB is "0", and this instruction is a single instruction. The operation designation designates the type of branch executed by this instruction, that is, the unconditional branch or the conditional branch, and the branch condition designation designates the condition for establishing the branch in the conditional branch. The branch destination instruction address is
The instruction address of the branch destination is given. The branch instruction is a single instruction and is executed only in the instruction execution unit 25 ₁ . The branch destination address DA is the instruction execution unit 25.
_It is given from ₁ to the program counter 29 and becomes an instruction address to be executed next at the time of branching. Figure 7
FIG. 6 is a diagram showing an instruction format of a multiple instruction format. Multiple instructions are executed by all instruction execution units 25 _{1 to} 25 _n.
In the above, a microinstruction address for executing a series of unique microinstruction sequences is designated.
The MSB is "1", indicating that this instruction is a multiple instruction. Portions other than the MSB are commonly output as microinstruction addresses to the microinstruction memories 23 ₁ to 23 _n . Micro instruction memory 23 _1-23
n reads a microinstruction from the commonly given microinstruction address S22, and the instruction execution units 25 _{1 to} 25 ₁
It is designed to supply to _n . The instruction execution unit 25 _1-2
In 5 _n, execute each microinstruction S23 ₁ ~S23 _n, respectively, so as to stop the execution of its own microinstruction at the time of running the predetermined microinstruction.

FIG. 8 is a diagram showing a microinstruction format. This format is used for the instruction execution units 25 ₁ to 2
It is common to all 5 _n . The most significant bit is a completion designation, and when a microinstruction with this bit being "1" is given, each instruction execution unit 25 _{1 to} 25 _n stops the execution of the microinstruction immediately after the execution of the instruction. , The execution end signals S25 _{1 to} S25 _n are output.
Further, when the microinstruction memory 23 ₁ to 23 _n reads a microinstruction whose completion designation is “1”, the microinstruction is newly read out unless a new multiple instruction S22 is given from the instruction register 22. The instruction execution units 25 ₁ to 25
Continue to give 5 _n . The source 1 designation and the source 2 designation of the microinstruction format designate the register number in the register file 26 for storing the data to be operated. The destination designation is to designate the register number in the register file 26 that is the storage destination of the operation result data.

Next, the operation of FIG. 1 will be described with reference to FIGS. 5, 6, 7, and 8. Program counter 29
The instruction code stored in the instruction memory 21 is read for each instruction execution cycle based on the instruction address S29 given by The read instruction code S21 is held in the instruction register 22 for one instruction execution time. The instruction code S21 held in the instruction register 22 is commonly output as the instruction code S22 to the microinstruction memories 23 ₁ to 23 _n and the selection circuit 24. Also, the instruction code S2
2 MSBs, that is, single / multiple instruction instruction code S22a,
It is output to each selection input terminal of the selection circuit 24 and the selection circuit 28. In the micro instruction memories 23 ₁ to 23 _n , when the single / multiple instruction instruction code S22a is “1” (that is,
Only in the case of multiple command instruction), simultaneously reads the microinstruction S23 ₁ ~S23 _n based on given microinstruction address. These microinstructions S23 _{1 to} S2
3 _n are instructions that are independently executed by the instruction execution units 25 _{1 to} 25 _n , and are unique micro instructions. The instruction execution unit 25 ₁ uses the single / multiple instruction instruction code S22a.
Either a single instruction or a microinstruction sequence for multiple instruction execution is executed depending on the logic level of The instruction execution units 25 _{2 to} 25 _n execute only microinstruction sequences for executing multiple instructions.

The selection circuit 24 receives the instruction code S22 directly given from the instruction register 22 and the micro instruction S23 ₁ read from the micro instruction memory 23 ₁ . The selection circuit 24 selects either the instruction code S22 or the microinstruction S23 ₁ as a selection signal using the single / multiple instruction instruction code S22a from the instruction register 22 and sends it to the instruction execution unit 25 ₁ . That is, when the single / multiple instruction instruction code S22a is "1", the instruction code S22 is a multiple instruction, and therefore the micro instruction S2.
When 3 ₁ is selected and the single / multiple instruction instruction code S22a is “0”, the instruction code S22 is a single instruction, and therefore the instruction code S22 is selected and given to the instruction execution unit 25 ₁ . Instruction execution unit 25 ₁ to 25 _n are register file input from 26 each source 1 data s1 ₁ ~s1 _n and the source 2 data s2 ₁ ~s2 _n, the result of each destination performs an operation on these Data d
It is stored in the register file 26 as s _{1 to} ds _n .

When the instruction code S22 is a single instruction,
Only the instruction execution unit 25 ₁ executes the instruction. At this time, the instruction execution units 25 _{2 to} 25 _n are in a state where the instruction execution is stopped. When the execution of a single instruction is completed in the instruction execution unit 25 ₁ , the execution end signal S25 ₁ is asserted (in the present embodiment, changes from logic “0” to logic “1”). The execution end signal S25 ₁ is input to the AND circuit 27 and the selection circuit 28. When the single / multiple instruction instruction code S22a is "0", that is, when the executed instruction is a single instruction, the selection circuit 28 selects the execution end signal S25 ₁ directly input from the instruction execution unit 25 _1. Then, it is output to the program counter 29 as an execution end signal S28. The program counter 29 advances the count value by one when the execution end signal S28 is asserted, and outputs the next instruction address S29. However, the instruction execution unit 25 ₁
If the instruction executed in step ₁ is a branch instruction, the value corresponding to the branch destination address DA input from the instruction execution unit 25 ₁ is output as the next instruction address S29.

When the instruction code S22 is a multiple instruction, each instruction execution unit 25 _{1 to} 25 _n executes one or a plurality of microinstruction sequences S23 _{1 to} S23 _n given at the same time.
That is, the instruction execution units 25 _{2 to} 25 _n have the microinstruction S2 read from the microinstruction memory 23 ₂ to 23 _n.
3 _{2 to} S23 _n are given respectively. Further, the microinstruction S23 ₁ is selected and input to the instruction execution unit 25 ₁ by the selection circuit 24. The MSB of the microinstruction shown in FIG. 7 is a completion designation bit, and each instruction execution unit 2
5 ₁ to 25 _n in the case of the complete specified bit is "0" continues to execute each microinstruction memory 23 _1-23 subsequent microinstruction sequentially input from _n S23 _{1 ~S23 n,} respectively. On the other hand, when the completion designation bit is "1", each execution end signal S2
Each of 5 _{1 to} S25 _n is output and the execution of the micro instruction is stopped. The microinstruction execution is performed by newly adding the microinstruction S23 from the microinstruction memories 23 ₁ to 23 _n.
It is restarted by giving _{1 to} S23 _n . In this embodiment, the time required to execute one microinstruction is common to all the instruction execution units 25 _{1 to} 25 _n and is one instruction execution time (for example, one clock cycle time).

The execution end signal S25 ₁ ~S25 _n outputted from the instruction execution unit 25 ₁ to 25 _n is asserted inherent time of each instruction execution unit 25 ₁ to 25 _n, respectively. The execution end signals S25 _{1 to} S25 _n are input to the AND circuit 27. The AND circuit 27 outputs the execution end signal S25 ₁
If all ～S25 _n is asserted, it asserts the multiple instruction execution end signal S27. The selection circuit 28 executes the multiple instruction execution (that is, the single / multiple instruction instruction code S22).
If a is "1"), the multiple instruction execution end signal S27 is selected and output to the program counter 29 as the execution end signal S28. In this way, when the multiple instruction is executed, the completion of all of the arbitrary number of microinstruction sequences executed by the instruction executing units 25 _{1 to} 25 _n is recognized, and the completion of execution of the multiple instruction itself is recognized. When the execution end signal S28 is asserted, the program counter 29 sets the count value to 1
And the instruction memory 21 as the next instruction address S29.
Output to.

As described above, in the first embodiment,
A single instruction to be executed only by the instruction execution unit 25 ₁ is read from the instruction memory 21, one specific to the respective instruction execution unit 25 ₁ to 25 _n to be executed simultaneously by the instruction execution unit 25 ₁ to 25 _n Multiple instructions that are expanded and executed in one or a plurality of microinstruction sequences are executed based on the program stored in the instruction memory 21. In the execution of multiple instructions, the length of each unique microinstruction sequence that is simultaneously executed by each of the instruction execution units 25 _{1 to} 25 _n is arbitrary, so that the execution from each of the instruction execution units 25 _{1 to} 25 _n in the AND circuit 27 is performed. By taking the logical product of the completion signals S25 _{1 to} S25 _n , the multiple instruction execution completion signal S27 is output and sent to the program counter 29. The next instruction address S29 is output from the program counter 29 to the instruction memory 21, and the instruction is executed at the next instruction execution time. Therefore, a certain one
In one program, for example, parallel processing such as vector calculation or loop execution is executed as multiple instructions, and sequential processing such as control processing based on a control sequence is executed as single instruction. You can maximize the performance.

In addition, each instruction execution unit 25 when executing multiple instructions
_{Since the} microinstruction sequence executed in _{1 to} 25 _n can be arbitrarily set, it becomes easy to perform a plurality of calculation processes on a plurality of data. For example, in each instruction execution unit 25 _{1 to} 25 _n , a pipeline-like calculation process (that is, a result calculated immediately before by an adjacent instruction execution unit as the next operation target data in the own instruction execution unit) (that is, , Software pipelining) in parallel. Further, in the parallel instruction processing device according to the present embodiment, it is not necessary to provide each register file in the conventional SIMD type instruction processing device of FIG. 2 in pairs with each instruction execution unit, so that the circuit scale is increased and the data consistency is improved. It is possible to solve the problems of waiting for processing between the instruction execution units for ensuring the above, increasing the circuit scale by providing a circuit necessary for the processing for data communication, and increasing the processing time. Furthermore, the parallel instruction processing apparatus according to this embodiment is provided with the micro-instruction memory 23 ₁ ~ 23 _n for storing each microinstruction code S23 ₁ ~S23 _n for the instruction execution unit 25 ₁ to 25 _n, the conventional FIG. MIMD of 4
Of an instruction code capacity for giving a unique instruction code to each instruction execution unit in a distributed instruction processing apparatus, particularly in executing a program portion that is a sequential process, a complicated and large-scale equivalent to the number of instruction execution units The problem that the instruction code must be stored in the instruction memory 11 is solved.

Second Embodiment FIG. 9 is a block diagram showing the configuration of a parallel instruction processing device according to a second embodiment of the present invention. Elements common to those in FIG. 1 are designated by common reference numerals. ing. This parallel instruction processing device is similar to the parallel instruction processing device of FIG.
have. The output side of the instruction memory 21 is connected to the input side of the instruction register 22. The output side of the instruction register 22 is commonly connected to the input sides of the microinstruction memories 23 ₁ to 23 _n , and is also connected to the instruction input terminal of the single instruction execution section 25S which is the first instruction execution section. There is. The single instruction execution unit 25S is composed of, for example, an ALU, and has a function of executing only a single instruction in one instruction execution time (for example, one clock cycle time). The output terminals of the microinstruction memory 23 ₁ ~ 23 _n are connected to each instruction code input terminal of the second instruction execution unit in which the instruction execution unit 25m ₁ ~25m _n. Instruction execution unit 25m ₁ ~25m _n be formed of, for example, ALU, and has a function of executing only the microinstruction. Each source 1 data input terminal s of the instruction execution unit 25m _{1 to} 25m _n
1, each source 2 data input terminal s2, and each destination data output terminal ds
Of each source 1 data output terminal s1, each source 2 data output terminal s2, and each destination data input terminal ds.

On the other hand, the execution end signal output terminal e ₁ to e _n of the instruction execution unit 25m ₁ ~25m _n are respectively connected to the input terminals of a multiple instruction execution end detection circuit (n + 1) input AND circuit 27A ing. Further, MSB output terminal of the instruction register 22, certain one input terminal of the AND circuit 27A, the single instruction / multiple instruction input of the instruction execution unit 25m ₁ ~25m _n, and a single command execution unit 25S Commonly connected to single command / multiple command input terminals.
Further, the MSB output terminal of the instruction register 22 is connected to the first input terminal of the 2-input OR circuit 32 via the inverter 31. The output terminal of the AND circuit 27A is OR
It is connected to the second input terminal of the circuit 32. The output terminal of the OR circuit 32 is connected to the clock input terminal ck of the program counter 29. Single instruction execution unit 25S
The branch destination address output terminal of the
It is connected to the count start value (initial setting value) input terminal of. The output terminal of the program counter 29 is connected to the address input terminal A of the instruction memory 21.

Next, the operation of FIG. 9 will be described. The parallel instruction processing device of FIG. 9 performs almost the same operation as the parallel instruction processing device of FIG. 1, except for the following points. That is, provided a single instruction execution unit 25S and the instruction execution unit 25m ₁ ~25m _n, when the instruction code S22 is single instruction is given only instruction codes S22 for a single instruction execution unit 25S runs, the instruction execution unit 25m ₁ ~25m _n not given instruction code S22. At this time, since the execution time of the single instruction is fixed to one instruction execution time (for example, one clock cycle time), the single instruction execution unit 25S
Does not output an execution end signal, and the single / multiple instruction instruction code S22a of "0" is ORed through the inverter 31.
It is input to the circuit 32 and is output from the OR circuit 32 to the program counter 29 as an execution end signal S32 of "1". Further, the instruction code S22 is the case of multiple instructions, the instruction execution unit 25m ₁ ~25m _n in the instruction code S22 is executed provided. When the execution of the instruction ends at the instruction execution unit 25m ₁ ~25m _{n, "1"} execution end signal S
25m ₁ ~S25m _n is output to the AND circuit 27A. At this time, since the single / multiple instruction instruction code S22a is "1", the AND circuit 27A outputs the multiple instruction execution end signal S27A of "1", and the multiple instruction execution end signal S27A is input to the OR circuit 32. The OR circuit 3
2 is output to the program counter 29 as the execution end signal S32 of "1".

As described above, in the second embodiment,
Since the single instruction execution unit 25S for executing only a single instruction and the instruction execution units 25 _{1 to} 25 _n for executing only a microinstruction sequence executed when executing multiple instructions are separately installed,
Single Instruction execute a single instruction execution unit 25S (e.g., logical operations, the flow of processing of a program) and the optimum configuration, simple such as a micro instruction execution (e.g. arithmetic operation instruction execution unit 25m ₁ ~25m _n The configuration can be optimized for calculation). Therefore, in the parallel instruction processing device according to the first embodiment, the instruction execution unit 25 ₁ in FIG. 1 needs to have a circuit configuration capable of executing both a single instruction and a micro instruction. Since the instruction execution unit 25S only needs to execute a single instruction, the circuit scale can be further reduced in addition to the advantages of the first embodiment.

[0028]

As described in detail above, according to the first invention, a single instruction read from the instruction memory and executed only by the first instruction executing section, and the first instruction execution Section and a plurality of second instruction executing sections are simultaneously executed by the first instruction executing section and each second instruction executing section. Instructions are executed based on a program stored in the instruction memory. In multiple instruction execution, the length of each unique microinstruction sequence that is simultaneously executed by each second instruction execution unit is arbitrary, so that all of the plurality of second instruction execution units complete execution of the multiple instructions. At this time, the multiple instruction execution end detection circuit outputs a multiple instruction execution end signal, which is sent to the program counter. The next instruction address is output from the program counter to the instruction memory, and the instruction is executed at the next instruction execution time. Therefore, in a certain program, for example, parallel processing such as vector calculation or loop execution is executed as multiple instructions, and sequential processing such as control processing based on a control sequence is executed as single instruction. Therefore, the processing performance of the program can be maximized.

Further, since it is possible to make an arbitrary microinstruction sequence executed in the first instruction execution unit and each second instruction execution unit at the time of execution of multiple instructions, a plurality of microinstructions can be provided for a plurality of data. Processing such as calculation processing is facilitated. For example, in the first instruction execution unit and each of the second instruction execution units, a pipe that uses the result calculated immediately before by the adjacent instruction execution unit as the next operation target data in the own instruction execution unit Line-like calculation processing (that is,
Software pipelining) can be easily performed in parallel. Moreover, in the parallel instruction processing device of the present invention,
Since it is not necessary to provide each register file in the conventional SIMD type instruction processing device in pairs with each instruction execution unit,
It is said that the circuit scale increases, the waiting of the processing between the instruction execution units for guaranteeing the consistency of the data, the circuit scale increase by providing the circuit necessary for the processing for the data communication, and the processing time increase. You can solve the problem. Further, since the parallel instruction processing device of the present invention is provided with each microinstruction memory for storing each microinstruction code for each second instruction execution unit, it is possible to use each of the instruction execution units in the conventional MIMD type instruction processing device. In order to increase the instruction code capacity for giving a unique instruction code, especially in the execution of a program part that is a sequential process, a complicated and large-scale instruction code equivalent to the number of instruction execution parts must be stored in the instruction memory. The problem can be solved.

According to the second invention, the first instruction executing section for executing only a single instruction and the plurality of second instruction executing sections for executing only the micro instruction sequence executed at the time of executing multiple instructions. In order to separately install the first and second instruction execution units, the first instruction execution unit has an optimal configuration for single instruction execution (for example, logical operation, processing of program flow, etc.), and the plurality of second instruction execution units are Instruction execution (for example, simple arithmetic such as four arithmetic operations)
It is possible to have an optimal configuration for. Therefore, in the parallel instruction processing device according to the first aspect of the invention, the first instruction execution part needs to have a circuit configuration capable of executing both a single instruction and a microinstruction, while the first instruction execution part according to the second aspect of the invention. Since the first instruction execution unit only needs to execute a single instruction, the circuit scale can be further reduced in addition to the effect of the first invention.

[Brief description of drawings]

FIG. 1 is a configuration block diagram of a parallel instruction processing device showing a first embodiment of the present invention.

FIG. 2 is a configuration block diagram of a conventional SIMD type instruction processing device.

FIG. 3 is a diagram showing an instruction format.

FIG. 4 is a configuration block diagram of a conventional MIMD type instruction processing device.

FIG. 5 is a diagram showing a single instruction format 1.

FIG. 6 is a diagram showing a single instruction format 2;

FIG. 7 is a diagram showing a multiple instruction format.

FIG. 8 is a diagram showing a microinstruction format.

FIG. 9 is a configuration block diagram of a parallel instruction processing device showing a second exemplary embodiment of the present invention.

[Explanation of symbols]

21
Instruction memory 29
Program counter 25 ₁ , 25S
First instruction execution unit 23 ₁ to 23 _n
Micro instruction memory 25 _{2 to} 25 _n , 25 m _{1 to} 25 m _n
Second instruction execution unit 27, 27A
AND circuit (multiple instruction execution end detection circuit)

Claims (2)

(57) [Claims] 1. A single instruction instruction code for instructing a single instruction to execute one instruction with one instruction, or a multiple instruction instruction code for instructing multiple instructions to execute a plurality of instructions with one instruction, and instruction execution An instruction memory for storing an instruction code for storing the instruction code, a program counter for designating an instruction code for sending and reading an instruction address to the instruction memory, and outputting a micro instruction code based on the instruction code read from the instruction memory A plurality of microinstruction memories, and when the instruction code read from the instruction memory is the single instruction, the single instruction corresponding to the instruction code read from the instruction memory by determining that the instruction code is the single instruction. Is executed to end the execution of the single instruction, the single instruction execution end signal is activated, and the instruction read from the instruction memory is read. When the instruction code is the multi-instruction, it is determined that the multi-instruction is the multi-instruction and one of the multi-instruction is executed based on the micro-instruction code from one of the plurality of micro-instruction memories. A first instruction executing unit for executing; and when the instruction code read from the instruction memory is the multiple instruction, it is determined that the multiple instruction is the multiple instruction, and the micro instruction code from each of the micro instruction memories is used for the determination. A plurality of second instruction execution units that execute multiple instructions, and a multiple instruction execution end signal when all of the first instruction execution unit and the plurality of second instruction execution units have finished executing the multiple instructions A multi-instruction execution end detection circuit that is active when the single-instruction execution end signal or the multi-instruction execution end signal is active. Parallel instruction processing apparatus incremented the next instruction address scan is characterized in that the arrangement to be sent to the instruction memory. 2. The instruction memory according to claim 1, the program counter according to claim 1, the plurality of microinstruction memories according to claim 1, and the instruction code read from the instruction memory when the single instruction is given. The first instruction execution unit that determines that the instruction is the single instruction and executes the single instruction corresponding to the instruction code read from the instruction memory in a predetermined one instruction execution time. A plurality of second instruction execution units; a multiple instruction execution end detection circuit according to claim 1; and a current instruction address incremented when the single instruction instruction code or the multiple instruction execution end signal is active. And a program counter for sending the instruction address of 1. to the instruction memory after the elapse of the predetermined one instruction execution time.