JPH11119995A - Device and method for processing data - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve efficiency in pipeline processing for reading processing data stored in a data memory and storing them again after bit operation. SOLUTION: The instruction for bit operation fetched by an instruction fetching means 31 is decoded by an instruction decoding means 32, an execution address is generated by an address generating means 33, the processing data are read from a data memory 201 by a data reading means 34. Then after the bit operation of the instruction has been executed by a bit operating means 35, these processing data are stored in the data memory 201 by a data storage means 36. Since only one instruction is adequate to be inputted corresponding to the bit operation, the capacity of a program is reduced and the load on its preparation can be reduced. The data processing of bit operation can be completed within six clocks and even when accessing the data memory 201 in the following data processing, temporary stop at a maximum of two clocks is adequate.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a data processing apparatus and method for executing data processing of a plurality of instructions in a pipeline manner.

[0002]

2. Description of the Related Art Conventionally, as a data processing device, there is a microprocessor which executes data processing of a plurality of instructions at high speed by a pipeline system. In pipelined data processing, multiple instructions are sequentially shifted and processed by hierarchical hardware, so even if the time required for processing one instruction is not reduced, it is necessary to process data for multiple instructions. Time can be reduced.

A data processing apparatus as described above is, for example,
"Computer Architecture Quantitative Approach Second Edition, David A. Patterson / John L. Hennessy." The data processing apparatus will be described below as a conventional example with reference to FIGS.

FIG. 8 is a schematic block diagram showing the hardware of the data processing device corresponding to the processing procedure of the pipeline, and FIG. 9 is a schematic diagram showing the format of instruction codes of various instructions. is there. FIG. 10 is a schematic diagram showing mnemonic codes for various bit operations.
9 is a schematic time chart showing a processing procedure of pipeline processing of nine instructions.

[0005] The data processing apparatus 100 exemplified here is composed of:
The system includes a data memory 101 for temporarily storing various processing data in an updatable manner, and a microprocessor 102 for executing various data processing. The microprocessor 102 has a 32-bit RISC (Reduced Instrument).
As shown in FIG. 8, predetermined hardware is physically provided, and five stages 1 to 5 are logically provided.

The instruction fetch stage 1, which is the first stage, includes a program counter 11, an instruction memory 12, an adder 13, a multiplexer 14, and the like, and fetches various instructions. The instruction decode stage 2, which is the second stage, includes a register file 15, a sign extender 16, and the like, and executes decoding of the instruction fetched in the instruction fetch stage 1 and reading from the register file 15. I do. Since the register file 15 is composed of 32 internal registers each having a 32-bit storage capacity, up to 32 32-bit instruction codes and processing data are separately stored.

[0007] The processing execution stage 3, which is the third stage, includes a zero determiner 17, multiplexers 18 and 19,
An ALU (Arithmetic and Logical Unit) 20 is provided. For example, when the instruction is a word / store, an execution address of processing data for performing bit operation is generated from the instruction decoded in the instruction decode stage 2, and the instruction is generated. If the instruction is a conditional branch, execute the data processing of the ALU operation on the processing data, and if the instruction is a conditional branch,
Execute the condition determination process.

A memory access stage 4, which is a fourth stage, includes a data memory 101 for temporarily storing various processing data in an updatable manner. For example, when an instruction is load / store, a processing execution stage is provided. 3 to access the data memory 101 with the execution address generated and read or write the processing data.

The write-back stage 5, which is the fifth stage, includes a multiplexer 21 and the like.
Then, the processing data read from the data memory 101 is stored in the register file 15 of the instruction decode stage 2 from the instruction decode stage 2.

[0010] The data processing apparatus 100 having the structure described above.
The instruction for executing various operations is set in a 32-bit instruction code format as shown in FIG.
Mnemonic codes for various bit operations are represented as shown in FIG.

For example, in the format of an I-type instruction code used for instructions such as load / store / immediate operation / conditional branch of processing data, the type of the instruction is set to 6-bit "Opcode" and the register file 15-3
One piece of identification data for reading processing data from the two internal registers is set in 5-bit “rs1”. Furthermore, the identification data of one internal register for storing the processing data is set to 5 bits of “rd”, and various data such as the offset value of the execution address and the immediate value to be processed are set to 16 bits of “immediate”. Is done.

In the format of an R-type instruction code used for an instruction such as data operation between registers, the type of the instruction is set to “Opcode” of 6 bits, and 32 internal codes of the register file 15 are stored. Read two processing data to be processed from the register.
Bits “rs1” and “rs2” are individually set. One internal register for storing the processed data of the arithmetic processing is set to 5-bit "rd", and various data such as the content of the arithmetic processing is set to 16-bit "func".

Further, in the format of an instruction code of the J type used for an instruction such as an unconditional branch, the type of the instruction is set to “Opcode” of 6 bits, and various data such as an offset for the program counter 11 is set to 1 bit.
Set to 6 bits “Offset added to PC”.

The data processing apparatus 100 having the above structure
Means that even if one data process consists of multiple instructions,
This is executed at high speed by a pipeline method. For example, as shown in FIG. 11, a bit operation of clearing the 22nd bit of specific processing data of the data memory 101 and a predetermined data processing of the processing data of the bit-operated data memory 101 are performed. In such a case, the data processing of nine instructions, that is, the five instructions of the first bit operation and the four instructions of the subsequent data processing, is sequentially executed in a pipeline manner.

In the data processing of the first instruction "LW" of the first bit operation, the instruction is fetched by the instruction fetch stage 1 and decoded by the instruction decode stage 2, and from this instruction, the data execution of the data memory 101 is performed by the processing execution stage 3. An execution address is generated. The processing data is read from the data memory 101 by the memory access stage 4 at the execution address, and the processed data is fed back to the instruction decode stage 2 by the write-back stage 5 and is temporarily stored in the register file 15.

Similarly, the second and third instructions "LHI, XOR
In the data processing of "I", operation data such as a mask pattern is set in the register file 15, and the fourth instruction "AN
In the data processing of D ″, the processing data read from the data memory 101 is bit-operated by the operation data.
In the data processing of the fifth instruction “SW”, the bit-processed processed data is stored again in the data memory 101 at the same address as that at the time of reading.
This means that the processing data stored in advance in 1 is bit-operated.

The data processing of each of the various instructions as described above consists of five stages corresponding to the five stages 1 to 5 of the data processor 100, respectively. And the data is processed in parallel in stages 1 to 5 of the data processing apparatus 100.

Therefore, the first bit operation consisting of five instructions is completed with data processing of "5.times.5 = 25" clocks in "5 + 5-1 = 9" clocks, and consists of the following four instructions. The second data processing is completed in eight clocks. Since these two processing operations are also continuously pipelined, data processing for a total of 45 clocks is completed in 13 clocks.

In this case, the data memory 101 and the microprocessor 102 are separate data processing devices 100.
However, such a data processing device (not shown) in which the data memory 101 and the microprocessor 102 are integrated has also been put to practical use at present. In addition, although the instruction memory 12 is illustrated as being integrated with the microprocessor 102, a data processing device (not shown) in which the microprocessor 102 and the instruction memory 12 are separate has been put to practical use.

[0020]

The data processing apparatus 100 as described above can execute data processing at high speed by pipeline processing, but executes bit operation, which is one data processing, as described above. You need three to five orders to do so. Therefore, the data memory 1
It is necessary to input a plurality of instructions in order to perform a bit operation on the processing data of No. 01, so that the improvement of the processing speed is not effective, and the capacity of the program is increased and the burden of creation is also increased.

In order to solve such a problem, for example,
In a data processing device (not shown) commercialized by the present applicant, data processing such as bit operation can be executed by one instruction. For this data processing device,
The bit manipulation instructions are “instruction fetch, instruction decode, address generation, data read, data creation,
The data is read from the data memory in the fourth data processing. The sixth data processing is performed by the fifth data processing. Bit operations are performed in the data processing, and stored in the data memory in the seventh data processing.

In the case of the above-described data processing device, data processing of bit manipulation can be executed by one instruction, but the processing execution stage is operated by the third, fifth, and sixth data processing. It is necessary to operate the memory access stage in the fourth and seventh processes.

That is, in the data processing of the bit operation described above, the processing execution stage operated in the third processing needs to be occupied until the sixth processing. Unable to use stage. For this reason, in the above-described data processing device, when the data processing of the bit operation is performed, the subsequent data processing needs to temporarily suspend the data processing for three clocks, and the operation efficiency of the pipeline processing is reduced.

The present invention has been made in view of the above-described problems, and has as its object to provide a data processing apparatus and method capable of reducing a decrease in the processing efficiency of a pipeline when a bit operation is performed. .

[0025]

According to one aspect of the present invention, there is provided a data processing apparatus which accesses a separate data memory for temporarily storing various kinds of processing data in an updatable manner in response to a bit manipulation instruction, and In a data processing device that reads processing data from, performs bit manipulation, and stores again,
An instruction fetch unit for receiving at least an input of an instruction for bit operation, an instruction decoding unit for decoding an instruction input to the instruction fetch unit, and an execution address of processing data for performing bit operation on the instruction decoded by the instruction decoding unit. Address generating means for generating, data reading means for reading processing data from the data memory at the execution address generated by the address generating means, and processing data read by the data reading means, decoded by the instruction decoding means. Bit operation means for executing a bit operation of the instruction, and data storage means for storing processing data bit-operated by the bit operation means in the data memory at an execution address generated by the address generation means. ing.

Therefore, when the instruction fetch means receives an input of a bit manipulation instruction, the instruction decoding means decodes the input instruction. When the address generating means generates the execution address of the processing data to be bit-operated from the decoded instruction, the data reading means reads the processing data from the data memory with the generated execution address. Since the bit operation unit performs bit manipulation of the instruction decoded by the instruction decoding unit on the read processing data, the data storage unit stores the bit-processed processing data with the execution address generated by the address generation unit. Store in data memory.

In other words, the data processing method of the above-described data processing device is formed by six-stage data processing of "instruction fetch, instruction decode, address generation, data read, bit manipulation, data write". The processed data read from the data memory by the data read is bit-operated by the fifth bit operation and then stored in the data memory by the sixth data write. Therefore, the data processing of the bit operation is executed in response to the input of one instruction, and the data processing of the bit operation is completed in six clocks. In addition, since the third-stage address generation and the fifth-stage bit manipulation are individually executed by dedicated means, the operation of occupying one processing stage among a plurality of data processes is the fourth stage. From the data read to the sixth-stage data write, and the subsequent data processing in the case of executing the bit operation may be suspended for at most two clocks.

The various means of the present invention as described above include:
What is necessary is just to be formed so as to realize the function, for example, dedicated hardware, a computer to which an appropriate function is provided by a program, a function realized inside the computer by an appropriate program, a combination thereof, and the like. Allow.

According to another data processing apparatus of the present invention, there are provided a data memory for temporarily storing various kinds of processing data in an updatable manner, an instruction fetch means for receiving at least an input of a bit operation instruction, and an instruction fetch means inputted to the instruction fetch means. An instruction decoding unit for decoding an instruction; an address generation unit for generating an execution address of processing data for performing bit operation from the instruction decoded by the instruction decoding unit; and an execution address generated by the address generation unit. Data reading means for reading processing data, bit operating means for performing bit operation of an instruction decoded by the instruction decoding means on the processing data read by the data reading means, and bit operation performed by the bit operating means The processing data is preceded by the execution address generated by the address generation means. And it includes a data storage means for storing in the data memory.

Therefore, when the instruction fetch means receives an input of a bit manipulation instruction, the input instruction is decoded by the instruction decode means. When the address generating means generates the execution address of the processing data to be bit-operated from the decoded instruction, the data reading means reads the processing data from the data memory with the generated execution address. Since the bit operation unit performs bit manipulation of the instruction decoded by the instruction decoding unit on the read processing data, the data storage unit stores the bit-processed processing data with the execution address generated by the address generation unit. Store in data memory.

That is, the data processing method of the above-described data processing device is formed by six-stage data processing of "instruction fetch, instruction decode, address generation, data read, bit manipulation, data write". The processed data read from the data memory by the read is bit-operated by the bit operation of the fifth stage, and then stored in the data memory by the data write of the sixth stage. Therefore, the data processing of the bit operation is executed in response to the input of one instruction, and the data processing of the bit operation is completed in six clocks. Further, since the third-stage address generation and the fifth-stage bit manipulation are individually executed by dedicated means, the operation of occupying one processing stage among a plurality of data processes is the fourth data operation. From the reading to the data writing in the sixth stage, the subsequent data processing in the case where the bit operation is executed may be temporarily stopped at a maximum of two clocks.

Another data processing apparatus of the present invention accesses a separate data memory for temporarily storing various kinds of processing data in an updatable manner in accordance with a bit manipulation instruction, and reads out the processing data from the data memory. In a data processing device that performs bit operation and then stores again, a data storage unit that temporarily stores various processing data in an updatable manner separately from the data memory, an instruction fetch unit that receives at least an input of a bit operation instruction, Instruction decoding means for decoding an instruction input to the instruction fetch means;
Address generating means for generating an execution address of processing data to be bit-operated from the instruction decoded by the instruction decoding means; and processing from one of the data memory and the data storage means using the execution address generated by the address generating means. Data reading means for reading data, bit operation means for executing bit operation of an instruction decoded by the instruction decoding means on the processing data read by the data reading means, and processing which has been bit-operated by the bit operation means Data storage means for storing data in one of the data memory and the data storage means with an execution address generated by the address generation means.

Therefore, when the instruction fetch means receives an input of a bit manipulation instruction, the instruction decoding means decodes the input instruction. When the address generation means generates an execution address of the processing data to be bit-operated from the decoded instruction, the data reading means reads the processing data from one of the data memory and the data storage means using the generated execution address. Since the bit operation unit performs bit manipulation of the instruction decoded by the instruction decoding unit on the read processing data, the data storage unit stores the bit-processed processing data with the execution address generated by the address generation unit. It is stored in one of the data memory and the data storage means.

That is, the data processing method of the above-described data processing device is formed by six-stage data processing of "instruction fetch, instruction decode, address generation, data read, bit manipulation, data write". The processed data read from one of the data memory and the data storage means by the data read is bit-operated by the fifth bit operation, and then is written to one of the data memory and the data storage means by the sixth-stage data write. Is stored. Therefore, the data processing of the bit operation is executed in response to the input of one instruction, and the data processing of the bit operation is completed in six clocks. In addition, since the third-stage address generation and the fifth-stage bit manipulation are individually executed by dedicated means, the operation of occupying one processing stage among a plurality of data processes is the fourth stage. From the data read to the sixth-stage data write, and the subsequent data processing in the case of executing the bit operation may be suspended for at most two clocks. In particular, since there are two bit manipulation targets, a data memory and a data storage means, if one is used for bit manipulation and the other is used for subsequent data processing, it is not necessary to suspend this subsequent data processing. Absent.

Another data processing apparatus according to the present invention comprises a data memory for temporarily storing various processing data in an updatable manner, and a data storage means for separately and temporarily storing various processing data in an updatable manner. Instruction fetch means for receiving at least an input of a bit-operated instruction, instruction decode means for decoding an instruction input to the instruction fetch means, and an execution address of processing data for bit-operating from the instruction decoded by the instruction decode means Address generating means for generating the data, data reading means for reading processing data from one of the data memory and the data storing means with the execution address generated by the address generating means, and processing read by the data reading means. A bit for performing a bit operation on an instruction decoded by the instruction decoding means on data Operating means, and data storage means for storing the processed data bit-operated by the bit operating means in one of the data memory and the data storage means at an execution address generated by the address generating means. I have.

Accordingly, when the instruction fetch means receives an input of a bit manipulation instruction, the instruction decoding means decodes the input instruction. When the address generation means generates an execution address of the processing data to be bit-operated from the decoded instruction, the data reading means reads the processing data from one of the data memory and the data storage means using the generated execution address. Since the bit operation unit performs bit manipulation of the instruction decoded by the instruction decoding unit on the read processing data, the data storage unit stores the bit-processed processing data with the execution address generated by the address generation unit. It is stored in one of the data memory and the data storage means.

That is, the data processing method of the above-described data processing device is formed by six-stage data processing of "instruction fetch, instruction decode, address generation, data read, bit operation, data write". The processed data read from one of the data memory and the data storage means by the data read is bit-operated by the fifth bit operation, and then is written to one of the data memory and the data storage means by the sixth-stage data write. Is stored. Therefore, the data processing of the bit operation is executed in response to the input of one instruction, and the data processing of the bit operation is completed in six clocks. In addition, since the third-stage address generation and the fifth-stage bit manipulation are individually executed by dedicated means, the operation of occupying one processing stage among a plurality of data processes is the fourth stage. From the data read to the sixth-stage data write, and the subsequent data processing in the case of executing the bit operation may be suspended for at most two clocks. In particular, since there are two bit manipulation targets, a data memory and a data storage means, if one is used for bit manipulation and the other is used for subsequent data processing, it is not necessary to suspend this subsequent data processing. Absent.

According to another data processing method of the present invention, a data memory for temporarily storing various kinds of processing data in an updatable manner is accessed in accordance with a bit manipulation instruction, and the processing data is read from the data memory to perform bit manipulation. In the data processing method of storing data again, an input of at least a bit operation instruction is received, the input instruction is decoded, and an execution address of processing data to be bit operated is generated from the decoded instruction. The processing data is read from the data memory at the execution address, the bit operation of the decoded instruction is performed on the read processing data, and the bit-processed processing data is stored in the data memory at the generated execution address. Stored.

Therefore, this data processing method is formed by six-stage data processing of "instruction fetch, instruction decode, address generation, data read, bit manipulation, data write". The read processed data is bit-operated by the bit operation of the fifth stage, and then stored in the data memory by the data write of the sixth stage. Therefore, the data processing of the bit operation is executed in response to the input of one instruction, and the data processing of the bit operation is completed in six clocks. In addition, since the third-stage address generation and the fifth-stage bit manipulation can be individually executed by dedicated means, the operation of occupying one processing stage among a plurality of data processes is the fourth data read operation. To the sixth stage data write,
The suspension of the subsequent data processing when the bit operation is executed may be at most two clocks.

According to another data processing method of the present invention, one of a data memory for temporarily storing various kinds of processing data in an updatable manner and a data storage means are accessed in response to a bit manipulation instruction, and In a data processing method for reading processing data from one of data storage means, performing bit manipulation, and then storing again, an input of at least a bit manipulation instruction is received, the inputted instruction is decoded, and the decoded instruction is An execution address of the processing data to be bit-operated is generated, the processing data is read from one of the data memory and the data storage means with the generated execution address, and the bit of the instruction decoded into the read processing data is generated. An operation is executed, and the bit-processed processing data is stored in the data memory at the generated execution address. It was set to be stored in one of the Li and the data storage means.

Therefore, this data processing method is formed by a six-stage data process of "instruction fetch, instruction decode, address generation, data read, bit manipulation, data write". The processed data read from one of the memory and the data storage unit is bit-operated by a fifth bit operation, and then stored in one of the data memory and the data storage unit by the sixth-stage data write. Therefore, the data processing of the bit operation is executed in response to the input of one instruction, and the data processing of the bit operation is completed in six clocks. Moreover, since the third-stage address generation and the fifth-stage bit manipulation can be individually executed by dedicated means, the operation of occupying one processing stage among a plurality of data processes is not required in the fourth stage. From the data reading to the sixth-stage data writing, the subsequent data processing when the bit operation is executed may be temporarily stopped at a maximum of two clocks. In particular, since there are two bit manipulation targets, a data memory and a data storage means, if one is used for bit manipulation and the other is used for subsequent data processing, it is not necessary to suspend this subsequent data processing. Absent.

[0042]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIGS. Note that the same portions as those of the conventional example described above with respect to the present embodiment are denoted by the same names, and detailed description is omitted.

FIG. 1 is a schematic block diagram showing the hardware of a data processing apparatus according to the present embodiment in accordance with the processing procedure of a pipeline. FIG. 2 is a block diagram showing the internal structure of a bit operator. 3 is a schematic diagram showing an instruction code format of an instruction, FIG. 4 is a schematic diagram showing mnemonic codes of various bit operations, and FIG. 5 is a schematic diagram showing a processing procedure of a pipeline processing of five instructions of two processing operations. It is a simple time chart.

The data processing device 200 of the present embodiment also
As shown in FIG. 1, a data memory 201 and a microprocessor 202 are provided similarly to the data processing device 100 described above, but unlike the data processing device 100 described above, six stages 31 to 36 are provided. Logically formed.

An instruction fetch stage 31, which is the first stage, corresponds to an instruction fetch means, and includes a program counter 41, an instruction memory 42, an adder 4
3, a multiplexer 44, etc., and fetch various instructions. The instruction decode stage 32, which is the second stage, corresponds to an instruction decode means, and includes a register file 45, a sign extender 46, etc., and decodes the instruction fetched in the instruction fetch stage 31 and registers the instruction in the register file 45. And read from.

The address generation stage 33, which is the third stage, corresponds to the address generation means,
7, the multiplexers 48 and 49, the ALU 50, and the like. For example, when the instruction is a bit operation, an execution address of processing data to be bit-operated is generated from the instruction decoded by the instruction decode stage 32.

The memory read stage 34, which is the fourth stage, corresponds to data reading means and includes multiplexers 51 and 52 and a data memory 201. For example, when an instruction is a bit operation, an address generation stage 3
3 with the execution address generated by the data memory 201
Read processing data from.

The bit operation stage 35, which is the fifth stage, corresponds to bit operation means, and includes a multiplexer 53, a bit operation device 54, and the like. The bit operation stage 35 stores the instruction in the register file 45 of the instruction decode stage 32 in the same manner as in the conventional case, for example, when the instruction is a conventional method, but in the memory read stage 34 when the instruction is a bit operation. The instruction data decoded in the instruction decode stage 32 performs bit operations on the processing data read from the data memory 201.

The memory write stage 36, which is the sixth stage, corresponds to data storage means. For example, when the instruction is a bit operation, the processed data bit-operated by the bit operation stage 35 is stored in the address generation stage 33.
And stores it in the data memory 201 with the execution address generated.

As shown in FIG. 2, the bit operation unit 54 of the bit operation stage 35 includes 32 bit conversion circuits 61, and the input wiring 62 of each of the 32 bit conversion circuits 61. And the output wiring 63 are connected in parallel to 32 output terminals and input terminals of the data memory 201.

The bit conversion circuit 61 has first and second bit selection circuits 64 and 65, respectively. The first bit selection circuit 64 is composed of, for example, a three-input multiplexer. In the first bit selection circuit 64, an input wiring 62 is connected to a first input terminal via an inverter 66, and an output circuit (“0” and “1”) is connected to a second third input terminal. (Not shown).

Since the output terminals of the instruction decode stage 32 are connected to the first to third control terminals of the first bit selection circuit 64 via three stages of pipeline registers, the first bit selection circuit 64 The circuit 64 outputs an inverted output of the bit of the processing data read from the data memory 201 and one of “0” and “1” in accordance with the decoded bit manipulation instruction.

The second bit selection circuit 65 comprises, for example, a two-input multiplexer. One input terminal is connected to the input wiring 62, and the other input terminal is the output terminal of the first bit selection circuit 64. Is connected. The second bit selection circuit 65 reads data from the data memory 201 because one of the two control terminals is connected to one of the output terminals of the instruction decode stage 32 via an inverter 67 via a pipeline register for three stages. One of the output processing data bit and the bit output by the first bit selection circuit 64 is output in accordance with the decoded bit operation instruction.

The data processing device 200 having the above structure
The instruction to execute various operations is set in the format of a 32-bit instruction code of bit operation as shown in FIG. 3, and mnemonic codes of various bit operations are expressed as shown in FIG.

That is, the format of the B-type instruction code used for the bit operation of the processing data, such as set / clear / inversion, is such that the type of the bit operation is set to 6-bit “Opcode” and the data memory 201 The identification data of one of the 32 registers of the register file 45 storing the base address of the execution address of the processing data to be bit-operated is set to 5 bits “rs1”, and the bit operation to the 32-bit processing data is performed. Is set to 5-bit “bit #”. The 16-bit signed immediate value that is the offset of the execution address is "imme
diate ”.

More specifically, here, one identification data of 32 registers of the register file 45 is set in “rs1”, and a parameter to be added to the data stored in the register is set to “immediate”. So, "rs
By adding the offset set to “immediate” to the base address of the register of the register file 45 specified by “1”, the execution address of the processing data for the bit operation of the data memory 201 is generated.

It should be noted that I-type used for instructions such as load / store / immediate operation / conditional branch of processing data, R-type used for instructions such as data operation between registers, and instructions such as unconditional branch. The instruction codes used, such as the J type, are the same as those in the related art, and are not directly related to the present invention, so that the description is omitted.

In the above-described configuration, the data processing device 200 of this embodiment also executes data processing by various instructions at high speed in a pipeline manner, similarly to the data processing device 100 described above as a conventional example. . For example, as shown in FIG. 5, when a bit operation of clearing the 22nd bit of the specific processing data in the data memory 201 is executed as the first processing operation, the data processing of the data processing apparatus 200 of the present embodiment is performed. In the method, one instruction for bit operation may be input.

In this case, a bit manipulation instruction is fetched by the instruction fetch stage 31 and decoded by the instruction decode stage 32, and an execution address of processing data to be bit manipulated by the address generation stage 33 is generated from the instruction. Memory read stage 3 at this execution address
4, the processing data is read from the data memory 201, and the processing data is bit-operated in accordance with the instruction decoded by the bit operation stage 35. The bit-processed processing data is stored in the memory write stage 3
At 6, the data is returned to the memory read stage 34, and is stored again in the data memory corresponding to the execution address.

The data processing method of the data processing device 200 according to the present embodiment is formed by the six-stage data processing of “instruction fetch, instruction decode, address generation, data read, bit manipulation, data write” as described above. The processed data read from the data memory by the fourth-stage data read is bit-operated by the fifth-stage bit operation, and then stored in the data memory by the sixth-stage data write.

For this reason, since only one instruction is required to execute the data processing of the bit operation, it is possible to reduce the capacity of the program to reduce the load of creation. Since the data processing of the bit operation can be completed in six clocks, the data processing speed can be improved.

However, the data processing device 2 of the present embodiment
Also in the data processing method of No. 00, one data memory 201 is used for the fourth stage data read and the sixth stage data write.
Therefore, it is not preferable to access the same address of the data memory 201 in the subsequent data processing from the start of the fourth-stage data read until the completion of the sixth-stage data write. That is, when accessing the data memory 201 in the data processing subsequent to the bit operation, it may be necessary to temporarily stop the data processing. However, the data processing may be temporarily stopped at a maximum of two clocks.

For example, as shown in FIG. 5 (a), the data memory 201
If the address does not access the memory at the second stage unlike the bit operation, there is no need to suspend the data processing. Can be completed in 10 clocks.

As shown in FIG. 5B, if there is no memory access at the first stage of the data processing subsequent to the bit operation and the same address of the data memory 201 is accessed at the second stage, Since the data processing only needs to be stopped for one clock, two data processings can be completed in 11 clocks.

Then, as shown in FIG. 5C, in the first stage of the data processing subsequent to the bit operation, the data memory 201
If the same address is accessed, the data processing is stopped up to 2 clocks. However, since the two data processings can be completed in 12 clocks, the data processing can be completed more quickly than the conventional 13 clocks. Can be terminated.

That is, the data processing device 2 of the present embodiment
In the data processing method of No. 00, the bit operation can be executed by one instruction, so that the capacity of the program can be reduced, the burden of creation can be reduced, and the speed of data processing can be improved. Thus, even when accessing the data memory 201, the data processing can be completed more quickly than the method of the conventional device.

The present invention is not limited to the above-described embodiment, but allows various modifications without departing from the gist of the present invention. For example, in the above-described embodiment, the data processing device 200 includes the separate data memory 201 and the microprocessor 202.
Although it is illustrated that they are formed by, for example, a data processing device (not shown) in which these are integrated can also be implemented. In addition, although the instruction memory 42 is illustrated as being integrated with the microprocessor 202,
It is also possible to implement a data processing device (not shown) in which this is separated.

In the above embodiment, the bit operation execution position is set as a bit operation instruction format as shown in FIG. 3 so that the bit operation can be performed on all the bits of the 32-bit processing data. It has been exemplified that “bit #” is set to 5 bits. However, there is a case where the bit operation requires only a specific 8 bits of the 32-bit processing data. In such a case, as shown in FIG. 6, "bit #" which sets the execution position of the bit operation is set. 3
It can be a bit. In this case, there is a 2-bit margin in the instruction code of the instruction. For example, the instruction code is set to “func” dedicated to setting the type of bit operation such as set / clear / inversion, and the signal indicating the type of bit operation is Generation can be facilitated.

Further, the data processing apparatus 200 of the above embodiment
Although the example in which the medium for storing the processing data to be bit-operated is one data memory 201, as shown in FIG. 7, the data storage means for storing the processing data to be bit-operated separately from the data memory 201 As SFR
(Special Function Registers) 71 may be provided to form the data processing apparatus 300.

More specifically, the data processing device 300
The microprocessor 301 also includes a data memory 201 and a microprocessor 301, and an SFR 71 is provided in a memory read stage 34 of the microprocessor 301 in parallel with the data memory 201. The SFR 71 has an input terminal connected to the address generation stage 33 and the memory write stage 36 via multiplexers 72 and 73 in the same manner as the data memory 201. The output terminals of the SFR 71 and the data memory 201 are connected to the bit operation stage 35. It is connected to the bit operator 54 via a multiplexer 74.

The data processing apparatus 300 having the above configuration
Can selectively perform bit operation on one of the processing data of the data memory 201 and the SFR 71. However,
If one of the data memory 201 and the SFR 71 is used in this bit operation and the other is used in the subsequent data processing, there is no need to temporarily stop the subsequent data processing. Can be completed.

In the data processing device 300 described above,
Although the microprocessor 301 having the SFR 71 and the data memory 201 are illustrated as being separate from each other, the microprocessor 301 having the SFR 71 is
And the data memory 201 may be integrated to form a data processing device.

[0073]

Since the present invention is configured as described above, it has the following effects.

The data processing apparatus according to the first aspect of the present invention
In a data processing device that accesses a separate data memory that temporarily stores various processing data in an updatable manner in accordance with a bit operation instruction, reads processing data from the data memory, performs bit operation on the data, and stores the data again, An instruction fetch unit for receiving at least an input of an instruction for bit operation, an instruction decoding unit for decoding an instruction input to the instruction fetch unit, and an execution address of processing data for performing bit operation on the instruction decoded by the instruction decoding unit. Address generating means for generating, data reading means for reading processing data from the data memory at the execution address generated by the address generating means, and processing data read by the data reading means, decoded by the instruction decoding means. Bit operation means for executing a bit operation of an instruction Data storage means for storing the processed data bit-operated by the port operation means in the data memory at the execution address generated by the address generation means, so that an instruction to be input for the bit operation is provided. Since only one is necessary, the load of creation can be reduced by reducing the capacity of the program, the data processing of the bit operation can be completed in 6 clocks, and even if the subsequent data processing accesses the data memory. Since the suspension is performed at a maximum of two clocks, the processing speed can be improved.

The data processing apparatus according to the second aspect of the present invention
A data memory for temporarily storing various types of processing data in an updatable manner, an instruction fetch unit for receiving at least an input of a bit operation instruction, an instruction decode unit for decoding an instruction input to the instruction fetch unit, and the instruction decode unit Address generation means for generating an execution address of processing data to be bit-operated from the instruction decoded in step 1, data reading means for reading processing data from the data memory with the execution address generated by the address generation means, and data reading means A bit operating means for performing a bit operation of the instruction decoded by the instruction decoding means on the processing data read out by the instruction decoding means; and an execution address generated by the address generating means by processing the bit data processed by the bit operating means. A data storage means for storing the data in the data memory, With the provision, only one instruction is input for the bit operation, so that it is possible to reduce the capacity of the program and the burden of creation, and complete the data processing of the bit operation in six clocks. Even if the subsequent data processing accesses the data memory, the suspension is performed at a maximum of two clocks, so that the processing speed can be improved.

The data processing apparatus according to the third aspect of the present invention
In a data processing device that accesses a separate data memory that temporarily stores various processing data in an updatable manner in accordance with a bit operation instruction, reads processing data from the data memory, performs bit operation on the data, and stores the data again, A data storage unit for temporarily storing various processing data in an updatable manner separately from the data memory; an instruction fetch unit for receiving at least an input of a bit operation instruction; and an instruction for decoding an instruction input to the instruction fetch unit Decoding means; address generation means for generating an execution address of processing data for performing bit operation from the instruction decoded by the instruction decoding means; and the data memory and the data storage means using the execution address generated by the address generation means. Data reading means for reading processing data from one of the A bit operating means for performing a bit operation of the instruction decoded by the instruction decoding means on the processing data read out by the instruction decoding means; and an execution address generated by the address generating means by the processing data bit-operated by the bit operating means. With the provision of the data memory and the data storage means for storing the data in one of the data storage means, only one command to be input for the bit operation is required, so that the capacity of the program can be reduced. The burden of creation can be reduced, the data processing of the bit operation can be completed in 6 clocks, and even if the subsequent data processing accesses the data memory, the pause can be at most 2 clocks. If one of the data storage means is used for bit manipulation and the other is used for subsequent data processing, There is no need to pause the sense, it is possible to improve the processing speed.

According to a fourth aspect of the present invention, there is provided a data processing apparatus comprising:
A data memory for temporarily storing various processing data in an updatable manner; a data storage means for temporarily storing various processing data in an updatable manner separately from the data memory; and an instruction fetch means for receiving at least an input of a bit manipulation instruction Instruction decoding means for decoding an instruction input to the instruction fetch means; address generation means for generating an execution address of processing data for performing bit operation from the instruction decoded by the instruction decoding means; Data reading means for reading processing data from one of the data memory and the data storage means with the generated execution address; and bits of an instruction decoded by the instruction decoding means into processing data read by the data reading means. Bit operation means for performing an operation, and bit operation performed by the bit operation means. And a data storage unit for storing the processed data in one of the data memory and the data storage unit at an execution address generated by the address generation unit. In the case where only one is necessary, the capacity of the program can be reduced and the burden of creation can be reduced, the data processing of the bit operation can be completed in 6 clocks, and the subsequent data processing accesses the data memory. However, the suspension can be performed at a maximum of two clocks. If one of the data memory and the data storage means is used for bit operation and the other is used for subsequent data processing, it is not necessary to suspend the subsequent data processing. Since there is no processing speed, the processing speed can be improved.

According to a fifth aspect of the present invention, there is provided a data processing method comprising:
In a data processing method of accessing a data memory for temporarily storing various processing data in an updatable manner in accordance with a bit operation instruction, reading processing data from the data memory, performing bit operation, and storing the data again, at least a bit operation is performed. Receives the input of the instruction, decodes the input instruction, generates an execution address of processing data for performing bit operation from the decoded instruction, reads processing data from the data memory with the generated execution address, A bit operation of the decoded instruction is performed on the read processing data, and the bit-processed processing data is stored in the data memory at the generated execution address. Since only one instruction needs to be input, it is possible to reduce the capacity of the program and reduce the burden of creation. The data processing of the bit operation can be completed in 6 clocks, and even if the subsequent data processing accesses the data memory, the pause is up to 2 clocks, so that the processing speed can be improved. it can.

According to a sixth aspect of the present invention, there is provided a data processing method comprising:
One of a data memory and a data storage means for temporarily storing various processing data in an updatable manner is accessed in response to a bit manipulation instruction, and processing data is read out from one of the data memory and the data storage means to read a bit. In the data processing method of storing data after operation, at least receiving an input of an instruction for bit operation, decoding the input instruction, generating an execution address of processing data for bit operation from the decoded instruction, The processing data is read from one of the data memory and the data storage means at the generated execution address, and a bit operation of a decoded instruction is performed on the read processing data. The generated execution address is stored in one of the data memory and the data storage unit. With this configuration, since only one instruction needs to be input for the bit operation, it is possible to reduce the program capacity by reducing the program capacity and complete the bit operation data processing in six clocks. Can,
Even when subsequent data processing accesses the data memory, the processing speed can be improved because the suspension is performed at a maximum of two clocks.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram illustrating hardware of a data processing device according to an embodiment of the present invention in correspondence with a processing procedure of a pipeline.

FIG. 2 is a block diagram showing an internal structure of a bit operator.

FIG. 3 is a schematic diagram showing a format of an instruction code of a bit operation.

FIG. 4 is a schematic diagram showing mnemonic codes for various bit operations.

FIG. 5 is a schematic time chart showing a processing procedure of pipeline processing of two instructions.

FIG. 6 is a schematic diagram showing a modification of the format of a bit operation instruction code.

FIG. 7 is a schematic block diagram illustrating hardware of a data processing device according to a modified example in correspondence with a processing procedure of a pipeline.

FIG. 8 is a schematic block diagram illustrating hardware of a data processing device of a conventional example in correspondence with a processing procedure of a pipeline.

FIG. 9 is a schematic diagram showing the format of instruction codes of various instructions.

FIG. 10 is a schematic diagram showing mnemonic codes for various bit operations.

FIG. 11 is a schematic time chart showing a processing procedure of pipeline processing of two instructions.

[Explanation of symbols]

31 instruction fetch stage corresponding to instruction fetch means 32 instruction decode stage corresponding to instruction decode means 33 address generation stage corresponding to address generation means 34 memory read stage corresponding to data read means 35 bit operation stage corresponding to bit operation means 36 Memory write stage corresponding to data storage means 71 SFR 200, 300 as data storage means Data processing device 201 Data memory

Claims (6)

[Claims] 1. Accessing a separate data memory for temporarily storing various processing data in an updatable manner in response to a bit manipulation instruction, reading the processing data from the data memory, performing bit manipulation, and storing again. In a data processing device, an instruction fetch unit that receives at least an input of an instruction for bit operation, an instruction decode unit that decodes an instruction input to the instruction fetch unit, and a process that performs a bit operation on the instruction decoded by the instruction decode unit Address generation means for generating an execution address of data; data reading means for reading processing data from the data memory with the execution address generated by the address generation means; and an instruction for processing data read by the data reading means. A bit for performing a bit operation on the instruction decoded by the decoding means Data processing means for storing processing data bit-operated by the bit operating means in the data memory at an execution address generated by the address generating means. apparatus. 2. A data memory for temporarily storing various processing data in an updatable manner, an instruction fetch means for receiving at least an input of a bit operation instruction, and an instruction decoding means for decoding an instruction input to the instruction fetch means. Address generation means for generating an execution address of processing data to be bit-operated from the instruction decoded by the instruction decoding means; data reading means for reading processing data from the data memory with the execution address generated by the address generation means; Bit operation means for executing bit operation of an instruction decoded by the instruction decoding means on the processing data read by the data reading means; and processing the bit data operated by the bit operation means by the address generation means. The data to be stored in the data memory with the generated execution address And a data storage unit. 3. Accessing a separate data memory for temporarily storing various processing data in an updatable manner in accordance with a bit manipulation instruction, reading the processing data from the data memory, performing bit manipulation, and then storing the data again. In the data processing apparatus, data storage means for temporarily storing various processing data in an updatable manner separately from the data memory; instruction fetch means for receiving at least an input of a bit manipulation instruction; and input to the instruction fetch means. Instruction decoding means for decoding an instruction; address generation means for generating an execution address of processing data to be bit-operated from the instruction decoded by the instruction decoding means; and an execution address generated by the address generation means; Data reading means for reading processing data from one of the data storage means; Bit operation means for performing bit operation of an instruction decoded by the instruction decoding means on the processing data read by the data reading means; and processing data bit-operated by the bit operation means generated by the address generation means A data storage unit for storing the execution address in one of the data memory and the data storage unit. 4. A data memory for temporarily storing various processing data in an updatable manner, a data storage means for temporarily storing various processing data in an updatable manner separately from the data memory, and inputting at least a bit operation instruction. Instruction fetch means for receiving an instruction, instruction decode means for decoding an instruction input to the instruction fetch means, address generation means for generating an execution address of processing data for performing bit operation from the instruction decoded by the instruction decode means, Data reading means for reading processing data from one of the data memory and the data storage means with the execution address generated by the address generating means; and decoding the processing data read by the data reading means with the instruction decoding means. Bit operation means for performing a bit operation of the executed instruction, and the bit operation Data storage means and, in that the data processing apparatus comprising a storing processing data bit manipulation in stage one of said data storage means and the data memory in the generated execution address by the address generating means. 5. A data processing method for accessing a data memory for temporarily storing various processing data in an updatable manner in accordance with a bit manipulation instruction, reading the processing data from the data memory, performing bit manipulation, and then storing the data again. Receiving at least an input of a bit operation instruction, decoding the input instruction, generating an execution address of processing data for performing bit operation from the decoded instruction, and using the generated execution address from the data memory. Processing data is read, a bit operation of an instruction decoded into the read processing data is performed, and the bit-processed processing data is stored in the data memory at a generated execution address. Data processing method. 6. Accessing one of a data memory and a data storage means for temporarily storing various kinds of processing data in an updatable manner in response to a bit manipulation instruction, and performing processing from one of the data memory and the data storage means. In a data processing method for reading data, performing bit manipulation, and then storing the data again, at least receiving an input of a bit manipulation instruction, decoding the input instruction, and executing an execution address of processing data for performing bit manipulation from the decoded instruction The processing data is read from one of the data memory and the data storage means at the generated execution address, and a bit operation of a decoded instruction is performed on the read processing data. The data memory and the data storage means at the execution address at which the processed data is generated. A data processing method characterized in that the data is stored in one of the following.