JPS6015969B2 - Microinstruction address generation method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a microprogram control system, and more particularly to a microinstruction address generation system for causing an executing microroutine to jump to an address in response to an instruction code.

Conventionally, methods for generating the start address of a microinstruction to jump to the execution microroutine of the instruction according to the instruction code include a method of using the instruction code almost as is and adding a predetermined fixed pattern to its upper address bits;
Alternatively, a method was used in which the instruction code was compressed by various means to narrow the address space and a predetermined fixed pattern was attached to the upper address bits of the same machine.

In either method, the microinstruction start address is determined from the instruction code using a unique method.

In the method of compressing instruction codes, the same microinstruction start address is finally generated from multiple different instruction codes, but after executing common processing steps, they each execute their own processing steps. Branch to microinstruction. Even in this case, if we focus on one instruction code, the microinstruction start address is determined from that instruction code using a unique method. On the other hand, a jump-on condition code (JC
) It is difficult to perform advance control in the execution process of conditional instructions such as instructions.

In a microprogram control device, for example, a JC instruction execution processing microprogram decodes the instruction after fetching the instruction and generates the start address of the execution microroutine according to the instruction code, as shown in FIG.
Here, the instruction code is JC, so when we jump to the beginning of the JC processing microroutine, a condition code test is executed as the first processing step, and depending on the result, we perform jump processing or processing to proceed to the next instruction in the next cycle. It is common to perform However, J.
Instructions such as C are used at a relatively high rate, for example in electronic exchange processing programs, accounting for approximately 15% of the usage, and it is desirable to shorten the processing steps from the viewpoint of processing power. SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a microprogram-controlled processing system capable of executing conditional jump instructions at high speed.

Another object of the present invention is to use a predetermined instruction code and a predetermined external state to generate the start address of a plurality of instruction execution microroutines from one instruction code. The purpose of the present invention is to provide a new concept microinstruction address generation method.

Still another object of the present invention is to pursue optimal division of functions between microprogram control and wiring logic control. Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a typical microprogram controlled bag.

1 is a main memory unit, and its issue data is stored in an instruction register 2 or a buffer register 3.

The instruction register 2 and buffer register 3 can send data to the operand bus 11 or 12, and can also write operation results from the result bus 13. General-purpose register group 4 and flip-flop group 5 are connected to operand bus 12 and can be written to from result bus 13. The arithmetic logic unit 6 receives the operand bus 11 and the operand bus 12 as inputs, and outputs the result to the result bus 13. Regarding the control section, the input data, ie, micro-instructions, from the control storage section 7 are set in the micro-instruction register 8, coupled to the micro-instruction field decoder 9, and various control signals are issued.

A part of the microinstruction register becomes one input of the microinstruction address generation section 20 as next microinstruction address data. Microinstruction address generation section 2 This includes interrupt address data 16 and console setting data 1.
7 and instruction code data 15 are also input as address data. The microinstruction address generation unit 20
As shown in the figure, one of the above four address data
It consists of a multiplexer 21 for selecting one of the multiplexers and a control storage address register 22 that receives the output of the multiplexer as input. In the multiplexer 21, one of the inputs connected to the input terminals 1, 2, and 3 is selected and becomes an output depending on the states of the select control terminals B and A. FIG. 3 shows a functional table of the multiplexer 21. Select control terminal B,
A is for microphone. It is controlled by the instruction address generation control circuit 30. The first input control line 34 to the microinstruction address control circuit 30 serves as one input to the OR circuits 31 and 32, and when the control line 34 is energized to '11', the respective select control terminals B , A, the output lines 37 and 38 of the OR circuits 31 and 32 are also energized to '1',
The multiplexer 21 selects the address data 17 connected to the input terminal 3.

Address data 17 is set from the console operation panel. The second input control line 35 to the microinstruction address control circuit 30 is inverted and input to the other input of the OR circuit 31 and one input of the AND circuit 33. The output of the AND circuit 33 serves as the other input of the OR circuit 32. Therefore, when the input control line 34 is set to '0' and the tense line 35 is activated to '11', only the output line 37 is activated to '11', and the multiplexer 21 selects the address data 16. The address data 16 is set as the start address of the microprogram interrupt processing routine. Next, the third input control line 36 of the microinstruction address control circuit 30 is connected to the other input of the AND circuit 33, and when the input control lines 34 and 35 are '0',
36 is activated to 11●, only the output line 38 is activated to '1', and the multiplexer 21 is activated to the address conversion circuit 40.
Select the output data 15 of . When the three input control lines 34, 35, and 36 to the control circuit 30 are all '0', the output lines 37 and 38 are also '0', and the multiplexer is set by a part of the microinstruction register. Select next microinstruction address data 14. The input control line 36 is normally issued for 73 cycles shown in FIGS. 5 and 6, that is, for instructing and controlling that the start address of the instruction execution microroutine according to the instruction code is set as the control storage address. be.

In the ~ cycle, the instruction execution microroutine start address is generated by converting the instruction code by the address conversion circuit 40'.The present invention mainly relates to this address conversion method. FIG. 4 is a detailed circuit diagram of the address translation circuit 40 in FIG. 2.

In FIG. 4, the lower 4 bits of the address are converted. The microinstruction address generation unit 20 generates 11 address bits from the high order: #A, #99, #8, #7, #6, #5.
．． #4, #3, #2, #1. #0 is input. In the address conversion circuit 40, address bits #A, #9, #8
Fixed pattern '001' to address bit #7,
Partial bit positions #F, #E, #D, #C of the instruction code of the instruction register are supplied to #6, #5, and #4, and to address bits #3, #2, #1, and #0. converts the instruction code and supplies the outputs of AND circuits 45, 46 and AND-OR circuits 47, 48, respectively. The above 11 address bits are sent to the multiplexer 21 as address data 15.
is supplied to One input of the AND circuits 45 and 46 and one input of the AND circuits of the AND-OR circuits 47 and 48 are supplied with bit positions #B, #A, and #B of the instruction register 2, respectively.
Supply #9 and #8. The output of the OR circuit 42 is supplied to the other inputs of the AND circuits 45 and 46 as a gate signal that is activated to ``1'' when an instruction code using 6 bits or 8 bits is detected. AND-
The output of the OR circuit 43 is supplied to the other inputs of the OR circuits 47 and 48 as a gate signal 11' which is activated when an instruction code using 8 bits is detected.
The other AND circuits of the AND-OR circuits 47 and 48 are connected to external state truths 51 and 52, the contents of which change depending on the calculation result, respectively, and the external states 51 and 52 are connected to the other input of the AND circuit. When an instruction code such as a jump-on instruction (JC) is detected that requires knowing the state of 52 before proceeding to the next process.'1
The output of the OR circuit 44, which is biased to 1, is supplied as a gate signal. The inputs of the OR circuits 42, 43, and 44 are connected to the corresponding outputs of the instruction code decoder 4i. It will be shown that by employing the above configuration, the speed of the JC instruction is increased.

FIG. 5 shows a conventional method, and FIG. 6 shows a JC instruction execution microflow and its required number of steps according to the method of the present invention. In FIG. 5, an instruction fetch requires machine cycles T and T2, and in the 73rd cycle, the instruction code of the fetched instruction is decoded to generate the start address of the execution microroutine of the JC instruction. 74
The cycle is the first processing step of the JC instruction execution routine, in which ON/OFF of the condition code is tested and branches depending on the state.

In the 75th cycle, the jump condition is satisfied when the condition code is ON, so the jump destination instruction address is set in the instruction sequence counter and an instruction fetch operation is performed.

Further, when the condition code is OFF, the jump condition is not satisfied, the contents of the instruction sequence counter are incremented, and the next instruction fetch operation is performed. In FIG. 6, when the instruction code is detected in three cycles, the OR circuit 44 in FIG. 4 is energized to '1', the external state 51 is fixed to '0' or '1', The ON or OFF state of the condition code is connected to the external state 52 to generate the start address of the JC instruction execution microroutine.

Therefore, there are two first processing steps in the JC instruction execution routine in the T4 cycle, depending on whether the condition code is ON or OFF, and in the T4 cycle, the jump destination instruction address or increment value is immediately set in the instruction sequence counter, respectively. Perform an instruction fetch operation. Comparing FIG. 5 and FIG. 6, the processing corresponding to ↑4 cycles in FIG. 5 can be executed in 73 cycles in FIG. 6, so the instruction execution time is shortened. As explained above, in a microprogram control device, when a predetermined instruction code is detected in a machine cycle that generates the execution microroutine start address of the instruction from the instruction code, the present invention not only generates the instruction code but also the necessary instruction code. By generating the start address of the execution microroutine for the instruction using the external state, a relatively large improvement in processing speed can be obtained with the addition of a small number of gates.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a general microprogram control device, Fig. 2 is a peripheral block diagram of a microinstruction address generation section, Fig. 3 is a functional diagram of a multiplexer, Fig. 4 is an address conversion circuit diagram in the present invention, and Fig. 5 is a block diagram of a general microprogram control device. 6 is a microflow diagram for executing a JC instruction according to the conventional method, and FIG. 6 is a microflow diagram for executing a JC instruction according to the present invention. 20... Microinstruction address generation section, 30.
...Microinstruction address control circuit, 40...
...Address conversion circuit. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6

Claims (1)

[Claims] 1. In a microinstruction address generation method that generates a start address of a microroutine for executing an instruction from an instruction code, a circuit that detects a predetermined instruction code is provided, and the above-mentioned predetermined address is generated in a machine cycle that generates the start address from the instruction code. A microinstruction address generation method characterized in that when an instruction code detection circuit detects a predetermined instruction code, a start address of an instruction execution microroutine is generated from the instruction code and predetermined external information at the time of the machine cycle.