JPS5850046A - Information processing device - Google Patents

Abstract

PURPOSE:To reduce the number of parts of a panel logic circuit part and to hold the reliability and to reduce the mounting space, by executing a microprogram routine for maintenance or diagnosis in a control storage by an operation processing device. CONSTITUTION:Commands for maintenance or diagnosis from panel command and panel data switches 103 and 104 of a maintenance panel operation and display part 1 are received by panel command and data registers 204 and 205 of a panel logic circuit part 2, and contents of registers 204 and 205 are selected by a panel data selector 206 and are applied to an operation processing device 3. The output of a timing controlling circuit 203 for the panel logic circuit part is applied to a timing controlling circuit 303, and the output of a control storage address generating circuit 202 for maintenance and diagnosis is applied to a control storage address selector 302. A program routine for maintenance or diagnosis in the logic circuit part 2 is executed in the device 3, thus reducing the number of parts of the circuit part 2 to improve the reliability.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a control memory and a first control memory address generation time for generating an address of the control memory for executing an instruction code or interrupt processing, etc. This invention relates to a microprogram-controlled information processing device equipped with an arithmetic processing unit.

In particular, the present invention relates to an information processing apparatus that is provided with a maintenance panel and controls writing or reading of data for maintenance or diagnosis to the arithmetic processing unit from the maintenance panel.

Generally, this type of information processing device is equipped with a maintenance panel for maintenance diagnosis or inspection during device development.

Conventionally, in the above-mentioned information processing apparatus.

The maintenance panel has a logic circuit section, and only by the operation of this logic circuit section, maintenance - writing of data for maintenance or diagnosis of the mother channel to the processing unit side or reading from the processing unit side is performed. was under control.

That is, in a conventional information processing device, the control memory in the arithmetic processing device stores only the microprograms for executing the above-mentioned normal instructions, and programs for maintenance or diagnosis are stored in the logic circuit section by the operator's operation. It was carried out in

However, as the scale of information processing equipment increases and the nine functions become more sophisticated, the functions required for maintenance/main channel reception have become multi-axial. Under such circumstances, if conventional maintenance or diagnostic functions were to be realized only by the operation of the logic circuit section of the maintenance/f channel, the logic circuit section would become larger to accommodate the complexity of the function.

As the logic circuit becomes larger, the number of parts increases, which leads to various disadvantages such as lower reliability, higher power consumption, larger installation space, and increased cost. Become.

An object of the present invention is to provide a second control storage address generation circuit for maintenance or diagnosis in the logic circuit section of the maintenance/f channel,
Obtain the start address of a maintenance routine given by the maintenance panel, and launch the arithmetic processing unit to the address, causing the arithmetic processing unit to execute the maintenance or diagnostic microprogram routine, thereby creating an information processing device in which the diagnostic function is realized. It is about providing.

According to the present invention, a control memory and a first control memory address generation Wm for generating an address of the control memory for normal instruction execution such as execution of an instruction code or interrupt processing.
A command register that receives commands for maintenance or diagnosis in an information processing apparatus equipped with an arithmetic processing unit having 'l.

A second control memory address generation circuit that generates a start address of a maintenance or diagnostic microzologram routine provided in the control memory from the command stored in the command register is provided separately from the arithmetic processing unit. A control memory address selector is provided in the logic circuit section provided in the control memory and selects one of the addresses generated by the first and second control memory address generation circuits and applies the selected address to the control memory. Provided in the processing equipment.

When the command is stored in the command register of the logic circuit unit, the arithmetic processing device controls the control memory address by selecting the address generated by the second control memory address generation circuit. An information processing device is obtained, which is characterized in that it executes the maintenance or diagnostic microprogram routine in its memory.

Next, embodiments of the present invention will be described with reference to the drawings.

□ FIG. 1 is a block diagram of an information processing device implementing the present invention. 1 is the operation/display section of the maintenance/4' panel, 2 is the logic circuit section of the maintenance panel, 3 is the arithmetic processing unit, 4 is the main storage device, and 5 is the input/output channel. Show the device.

The operation/display section 1 of the maintenance panel includes two display devices 101,
A control switch 102, a maintenance/diagnosis command switch 103, and a 7' switch 104 are provided.

The logic circuit section 2 of the maintenance panel includes a display register 201 that holds 9 display data, a main channel command register 204 that temporarily stores panel commands for maintenance and diagnosis, and a panel data register 205 that temporarily stores panel data. , /4? The contents of the panel command register 204 or the contents of the panel data register 205 are selected and □sent to the arithmetic processing unit 3, and the contents of the panel command register 204 are selected and the contents of the panel command register 204 are used for maintenance and diagnosis. Maintenance and
The diagnostic control memory address generation circuit 202 and the entire panel logic circuit section, especially the address generation circuit 202. which is activated by the panel control switch 102, A panel logic circuit unit for controlling the selector 206 and the timing control circuit 303 in the arithmetic processing unit is provided. ° control storage address generation circuit 301;
This control storage address generation circuit 301 provides:
The control memory address or maintenance/diagnosis control memory address generation circuit 202, the control memory address selector 302 that selects a given control memory address, and the timing control circuit 303 are used for normal instruction execution and maintenance/diagnosis command execution. A control memory 304 and a control memory output register 305 used for both are provided.

The operation will be explained in detail below. First, set commands for maintenance and diagnosis on the / mother channel command switch 103,
If the command is a write type command and requires write data, set the panel data to the panel data switch 104.

The control switch 102 sends an activation signal to the timing control circuit 203. Upon receiving the activation signal, the timing control circuit 203 instructs the control memory address generation circuit 202 to generate a start address for the maintenance/diagnosis routine in the corresponding control memory 304 from the contents of the panel command register 204 (not shown). (b) When the address is generated, it is instructed via the calculation timing control circuit 303.

The timing control circuit 303 is instructed to execute a microinstruction from the control storage address specified as above. If the command is a write type command, it is switched from the panel command register 204 to/or the channel data register 205 at an appropriate timing according to instructions from the panel data selector 206a and the timing control circuit 203 (not shown). There is no need to particularly explain.

In this manner, maintenance and diagnosis commands set from the panel are executed in the processing unit using the maintenance and diagnosis microprogram routines in the control memory.

If the command is a read type command, it is finally taken into the display register 201 in the panel logic circuit section and displayed on the display device 101 of the A' panel operation/display section.

In addition, in executing panel commands as described above, there may be a common routine used for normal command execution within the maintenance/diagnosis routine itself, or multiple routines may be used to execute a single panel command. maintenance and diagnostic routines may be used in series.

As explained above, the present invention relates to the execution of maintenance/diagnosis commands set from the maintenance panel.

A second control memory address generation circuit provided in the panel logic circuit section obtains the start address of a maintenance or diagnostic microprogram routine in the control memory corresponding to the command, and causes the arithmetic processing unit to execute the routine. As a result, reliability is maintained without increasing the number of parts in the mother panel logic circuit section, and costs are kept low without increasing the power consumption and mounting space of the panel logic circuit section. Complex panel functions can be realized.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention. DESCRIPTION OF SYMBOLS 1...Maintenance panel operation/display section, 1o1...Display device, 102...Control switch, 1o3.../Main channel command switch, 1o4...Panel data switch. 2... Panel logic circuit section, 2o1... Display register. 202: Control storage address generation circuit for maintenance and diagnosis. 203...Panel logic circuit section timing control circuit. 204-Panel command register, 2o5-Panel data register, 206-Panel data selector, 3-Arithmetic processing unit, 301-Controllable storage address generation circuit, 302-Controlled storage address selector. 303...Timing control circuit, 3o4...Control memory. 305... Control memory output register, 4... Main memory device. 5...I/O channel device.

Claims (1)

[Claims] 1. Information comprising an arithmetic processing unit having a control memory and a first control memory address generation circuit l that generates an address of the control memory for executing an instruction code or executing an interrupt processing, etc. In the processing device, a command register receives a command for maintenance or diagnosis, and a second command register generates a start address of a maintenance or diagnosis microprogram routine provided in the control memory from the command stored in the command register. A control storage address generation circuit is provided in a logic circuit section provided separately from the arithmetic processing device, and one of the addresses generated by the first and second control storage address generation circuits is selected. The arithmetic processing device is provided with a control storage address selector that provides the control storage address selector to the control memory, and when the command is stored in the command register of the logic circuit unit, the arithmetic processing device 2. An information processing apparatus characterized in that the maintenance or diagnostic microzorodarum routine in the control memory is executed by selecting an address generated by the control memory address generation circuit of No. 2.