JPH04274520A - Microprogram controller - Google Patents

Abstract

PURPOSE:To improve the reliability of a microprogram controller by eliminating the occurrence of soft errors which are produced in a control storage at the time of executing an NOP instruction. CONSTITUTION:Address decoders 11 and 12 detect whether or not the specific addresses of control storages 9 and 10 storing NOP instructions which do not issue any operating instruction are supplied. When the decoders 11 and 12 detect whether the specific addresses are supplied or not, selection circuits 13 and 14 select NOP instructions prepared by means of hardware instead of the NOP instructions read out from the storages 9 and 10.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprogram control device, and more particularly to a microprogram control device in which a plurality of control memories operate mutually exclusively.

0002

2. Description of the Related Art Conventionally, in this type of microprogram control device, the first step address of each instruction whose opcode in the instruction word is decoded or the address of a NOP instruction that does not issue any operation instruction is set to the operation mode. Therefore it is selected. By supplying the selected address to a plurality of control memories, each control memory is activated or placed in an idle state.

That is, as shown in FIG. 2, when the opcode 101 in the instruction word stored in the instruction register 1 is decoded by the decoder 2, the operation code 101 in the first step control memory 9, 10 for each decoded instruction is address 102
and mode signal 103 are output from decoder 2 to address selection circuits 3 and 4. Address selection circuit 3, 4
are the address 102 from the decoder 2 and the address (HWNOP) 122 in the control memories 9 and 10 of the NOP instruction generated by hardware (not shown), respectively.
123 and mode signal 1 from decoder 2.
Select according to 03. Address selection circuit 3, 4
The selected addresses 104 and 105 are supplied to control memories 9 and 10 via address registers 5 and 6 and address selection circuits 7 and 8. Addresses 108 and 109 from address selection circuits 7 and 8 are stored in control memories 9 and 10.
is supplied, the microinstructions 110 and 111 read from the control memories 9 and 10 are stored in the control data register 15.
, 16 to the arithmetic units 17 and 18.

Here, the control memory 9 stores a microprogram for controlling an arithmetic unit 17 that executes decimal arithmetic instructions and variable length arithmetic instructions. In addition, control memory 1
0 stores a microprogram for controlling the arithmetic unit 18 that executes processes other than those described above, such as basic arithmetic instructions. These control memories 9, 10 operate mutually exclusively. In other words, during the processing operation of the microprogram in the control memory 9, the microprogram in the control memory 10 is
P Execute command. Further, during the processing operation of the microprogram in the control memory 10, the microprogram in the control memory 9 executes a NOP instruction.

Now, when executing decimal arithmetic processing, the operation code 101 in the instruction word stored in instruction register 1 is
When decoded by the decoder 2, the address 102 of the control memory 9 storing the first step of the microprogram for executing the decimal arithmetic processing is outputted from the decoder 2 to the address selection circuits 3 and 4. At this time, since the mode signal 103 from the decoder 2 indicates the operation of the arithmetic unit 17, the address selection circuit 3 selects the address 102 from the decoder 2 and sends the address through the address register 5 and the address selection circuit 7. control memory 9
Output to. Further, the address selection circuit 4 selects the address 123 of the control memory 10 that stores the NOP instruction,
The address is output to control memory 10 via address register 6 and address selection circuit 8.

Note that the address selection circuits 7 and 8 select the addresses 106 and 107 from the address registers 5 and 6 and the second and subsequent steps of the microprogram in the next address field of the microinstruction stored in the control data registers 15 and 16. Addresses 119 and 121 are selected. In this case, address selection circuits 7 and 8 select addresses 106 and 107 from address registers 5 and 6, respectively.
is selected and the address is supplied to the control memories 9,10.

Address 108 from address selection circuit 7
A microprogram for operating the arithmetic unit 17 is read from the control memory 9, and the microprogram is stored in the control data register 15. Further, the NOP instruction is read from the control memory 10 according to the address 109 from the address selection circuit 8, and the NOP instruction is stored in the control data register 16. For this reason,
Since the microprogram is input to the arithmetic unit 17 as control data 118 from the control data register 15, the arithmetic unit 17 executes decimal arithmetic processing. Also,
Since the NOP instruction is input to the instruction arithmetic unit 18 as the control data 119 from the control data register 16, the arithmetic unit 18 does not execute arithmetic processing.

In such a conventional microprogram control device, when the address where the NOP instruction is stored is selected by the address selection circuits 3 and 4, the NOP instruction read from the control memories 9 and 10 by the address is selected. It is executed by arithmetic units 17 and 18. When a fault due to a soft error occurring in the control memories 9 and 10 is detected in this NOP instruction, if the fault is a correctable error, the NOP instruction is executed by correcting it; In this case, the device must be stopped, which has the disadvantage of reducing reliability.

[0009]

[Object of the Invention] The present invention has been made in order to eliminate the drawbacks of the conventional ones as described above, and improves reliability by eliminating failures caused by soft errors that occur in control memory when executing NOP instructions. The object of the present invention is to provide a microprogram control device that can perform the following tasks.

0010

SUMMARY OF THE INVENTION A microprogram control device according to the present invention is a microprogram control device having a control memory for storing a microprogram, and address supply means for indicating an address of the control memory, wherein detecting means for detecting whether or not the address indicates a specific address; and detecting one of a microinstruction read from the control memory and a specific instruction generated by hardware according to the detection result of the detection means. The present invention is characterized in that it includes a selection means for selecting.

Another microprogram control device according to the present invention includes a plurality of control memories each storing a different microprogram and operating mutually exclusively, and a plurality of control memories provided corresponding to each of the plurality of control memories. A microprogram control device having a plurality of address supply means for instructing an address of each of the control memories, the microprogram control device being provided corresponding to each of the plurality of control memories, and the address from the address supply means instructing a specific address. a plurality of detection means for detecting whether or not the above-mentioned control memory is present; The method is characterized in that it includes a plurality of selection means for selecting one of the specific command and the specific command.

0012

[Embodiment] Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In the figure, a microprogram control device according to an embodiment of the present invention includes address decoders 11, 1.
The configuration is the same as that of the conventional example shown in FIG. 2 except that 2 and selection circuits 13 and 14 are provided, and the same components are given the same reference numerals. Further, the operations of these same components are similar to those of the conventional example.

Address decoders 11 and 12 decode addresses 108 and 109 from address selection circuits 7 and 8, and select specific addresses in control memories 9 and 10 in which NOP instructions that do not issue any operation instructions are stored. Detect whether or not it has been supplied. Address decoders 11 and 12 output the detection results to selection circuits 13 and 14 as decoded signals 112 and 113.

Selection circuits 13 and 14 are address decoders 1
In accordance with the decode signals 112, 113 from the control memories 9, 10, one of the microinstructions 110, 111 read from the control memories 9, 10 and the NOP instructions 114, 115 generated by hardware (not shown) is executed. select. The selection circuits 13 and 14 transfer the selected microinstructions 116 and 117 to control data registers 15 and 16.
The data is output to arithmetic units 17 and 18 via.

Next, the operation of one embodiment of the present invention will be explained using FIG. For example, when executing decimal arithmetic processing, when opcode 101 in the instruction word stored in instruction register 1 is decoded by decoder 2,
The address 102 of the control memory 9 storing the first step of the microprogram for executing decimal arithmetic processing is output from the decoder 2 to the address selection circuits 3 and 4.

At this time, mode signal 1 from decoder 2
Since 03 indicates the operation of the arithmetic unit 17, the address selection circuit 3 selects the address 102 from the decoder 2 and outputs the address to the address register 5. Further, the address selection circuit 4 selects the address 123 of the control memory 10 that stores the NOP instruction, and outputs the address to the address register 6.

Addresses stored in address registers 5 and 6 are selected by address selection circuits 7 and 8, respectively, to designate addresses in control memories 9 and 10. At this time, at the same time, the addresses 108 and 108 selected by the address selection circuits 7 and 8
109 is decoded by address decoders 11 and 12. Since the address decoder 11 does not detect that the specific address of the control memory 9 in which the NOP instruction is stored is supplied, the selection circuit 13
Control memory 9 according to the decoded signal 112 from 1
The microinstruction 110 for performing decimal arithmetic processing read from the microinstruction 110 is selected. In addition, the address decoder 12
Since the selection circuit 14 detects that a specific address of the control memory 10 in which the NOP instruction is stored is supplied, the selection circuit 14 outputs the decode signal 11 from the address decoder 12.
3 read from control memory 10 according to
Instead of an instruction, a hardware generated NOP instruction 115 is selected.

The microinstructions 116 and 117 selected by the selection circuits 13 and 14, respectively, are stored in the control data register 15.
, 16. Therefore, the arithmetic unit 17 receives 10 as the control data 118 from the control data register 15.
Since a microinstruction for performing decimal arithmetic processing is input, the arithmetic unit 17 executes decimal arithmetic processing. Furthermore, since the NOP instruction generated by hardware is input to the arithmetic unit 18 as the control data 119 from the control data register 16, the arithmetic unit 18 does not perform any arithmetic processing.

In this manner, when the address decoders 11 and 12 detect that a specific address of the control memories 9 and 10 in which the NOP instruction is stored is supplied, the NOP instruction read from the control memories 9 and 10 is The circuits 13 and 14 select a NOP instruction generated by hardware instead of
By selecting the NOP instruction and outputting it to the arithmetic units 17 and 18, the control memory 9
, 10 can be eliminated. Therefore, the reliability of the microprogram control device can be improved.

In one embodiment of the present invention, the operation of a microprogram control device having control memories 9 and 10 that operate mutually exclusively has been described, but a microprogram control device having only one control memory has been described. It is obvious that it can be applied to, and is not limited to, this.

[0022]

As explained above, according to the present invention, when it is detected that the address supplied to the control memory indicates a specific address, the microinstruction read out from the control memory according to the detection result is By selecting and outputting a specific instruction generated by hardware instead of the NOP instruction, it is possible to eliminate problems caused by soft errors that occur in the control memory when executing the NOP instruction.
This has the effect of improving reliability.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a block diagram showing the configuration of a conventional example.

[Explanation of symbols]

3, 4, 7, 8 Address selection circuit 9,10 Control memory 11, 12 Decoder 13, 14 Selection circuit 17, 18 Arithmetic device

Claims (2)

[Claims] 1. A microprogram control device comprising a control memory for storing a microprogram, and address supply means for specifying an address of the control memory, comprising:
a detection means for detecting whether the address from the address supply means indicates a specific address; a microinstruction read from the control memory according to the detection result of the detection means; and a specific instruction generated by hardware. 1. A microprogram control device comprising: selection means for selecting one of the following. 2. A plurality of control memories each storing different microprograms and operating mutually exclusively; and a plurality of control memories provided corresponding to each of the plurality of control memories and instructing the address of each of the plurality of control memories. a microprogram control device having address supply means, the microprogram control device having a plurality of address supply means provided corresponding to each of the plurality of control memories for detecting whether or not an address from the address supply means indicates a specific address; a detection means, and is provided corresponding to each of the plurality of control memories, and selects one of a microinstruction read from the control memory and a specific instruction generated by hardware according to the detection result of the detection means. A microprogram control device comprising a plurality of selection means.