JPS60193047A - Mode checking system of microprogram - Google Patents

Abstract

PURPOSE:To obtain the detailed information on a parity error to use it as a decisive data for error processing by detecting the error bit information on a microinstruction in case a parity error is detected when a microprogram is loaded. CONSTITUTION:The data on a bus BUS is fetched to a processor U1 together with a microprogram. A control memory CS stores the microprogram with its address given from an address generating circuit ADD. An arithmetic and logic unit ALU uses the outputs given from switches MX1 and MX2 as an operand and a number to be operated respectively and performs an operation in response to an arithmetic type-based designation signal to store the arithmetic result to a register file RF. Furthermore the unit ALU performs an exclusive OR operation in an FETCH cycle between the contents of a microregister MIR and those of a register REG. Based on this arithmetic result, an error bit becomes clear.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a microprogram load check method, and particularly to a microprogram load check method when a microprogram with parity is loaded into one of a plurality of processors connected by a bus according to instructions from another processor. Regarding the load check method.

[Technical background] - In general, in data processing devices (hereinafter referred to as processors) using a microprogram control method, there are two types: ROM is used as a control memory for storing microprograms, and AM is used as a control memory for storing microprograms. be. The purpose of using RAM is to provide flexibility to the system, which is often done.

However, ILAM has lower reliability than general logic elements. Needless to say, the reliability of the microprogram is extremely costly to the system, and requires that the microprogram be authentically written into and retrieved from the control memory.6 When using RAM as the control memory, Microprograms are generally loaded by instructions from other processors during system initialization, and at this time a microprogram load check is performed.

[Prior art]

Conventionally, this type of microprogram load check involves adding a parity bit to the microinstruction and using the RA
Each time a micro-instruction is written to M, the written micro-instruction is read out, and parity is checked at this time. If a parity error is detected as a result of the parity check, the processor either stops operating or reports the detection of a parity error to the host device.

In such conventional methods, it is only possible to know that a parity error has been detected and the RAM address at that time, but it is difficult to know which bit of the microinstruction is in error, which poses a problem in error handling. It has the disadvantage of causing damage.

[Purpose of the invention]

An object of the present invention is to eliminate the above-mentioned drawbacks by simply adding a small amount of hardware, and when parity 1 is detected when loading a microprogram, by detecting the error bit information of the microprogram, the parity The aim is to obtain false information about errors and use them as decisive information in dealing with errors.

[Structure of the invention]

The method of the present invention is a microprogram load check method when a microprogram with parity is loaded into one of a plurality of processors connected to a bus according to instructions from another processor. , a register that holds data input to the processor from the bus; a control memory into which the microprogram is written in microinstruction units via the register; and a microinstruction memory into which the microinstruction is read out from the control memory for each write. a parity check circuit that performs a parity check when the microinstruction is input to the microinstruction register; and a parity check circuit that performs a parity check when a parity error is detected as a result of the parity check; An exclusive OR operation circuit is used for the microinstructions held by each of the registers, and the foreground register and the microinstruction register correspond to the same four-microinstruction step until the exclusive OR operation is performed. The present invention is characterized in that the above-mentioned load instruction is carried out so that the micro-instruction is retained, and the above-mentioned read instruction is carried out.

〔Example〕

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing the main part of the present invention. Referring to FIG. 1, this embodiment includes a decoder DEC, an address generation circuit ADD, a register BEG, and a RAM.
Il, a memory cs, a microinstruction register MIR, a parity tick circuit PC, a parity error generation circuit PE, and two switching BMx1 and 'Mx2.
．． , a microprogram control processor U1, a processor U2, and a main memory MM, which are composed of a performance device ALU, a performance control circuit ALC, a register file RF, a correction stop circuit DT, and a buffer circuit BF. Connected to bus BUS. .

The data on bus BU8, including the microprogram,
The data is taken into the processor U1 via the register REG. System 1 5cs is a RAM for storing a microprogram, and its address is generated by an address generation circuit Ai)D. Address generation port %AD
Df-J, the decoder DEC reads the command CMD from the processor U2, responds to the large result, and sends the address signal A.
D8t-1 is produced. The decoder DEC also has registers) 1. For EG, control commands to merge data with bus BU8. Register 几H for memory C8
It is possible to output signals for respectively instructing the loading of the contents held in G.

The microinstructions of the microprogram stored in the control memory are programmed into the register MI in the order θ' and are used to control operations in the processor U1. , the arithmetic override circuit ALC is also one of the circuits that uses the i-micro command and the contents held in the register MI, and uses the i-micro command and the contents held in the register MIR and the parity error signal from their parity error generation circuit PE. In response to E8, a switching signal XS of the 91 switchers MX1 and MX2;
Generates an operation type designation signal A8 for the arithmetic unit ALU and an address signal for the register file RF.

When the parity error signal E8 does not occur, the switches MXI and MX2 respond to the switching signal XS to change the contents held in part of the microinstruction register or the register file RF, and the contents held in the register REG or register file RP. accept. On the other hand, when the parity error signal E8 is generated, the switches MXI and MX2 each accept all bits of the microinstruction register MIR and the contents held in the register BEG in response to the switching signal XS.

The performance unit ALU converts each output from the switching devices MX1 and MX2 into a performance number, and performs an operation as a number in response to the operation type designation signal As. The calculation result in the calculation unit ALU is
Stored in register file RF. As described above, the content held in the register file RF becomes one input of the switch MX1, and can also be output to the bus BυS via the buffer circuit BP.

As mentioned above, the register BEG and the microinstruction register MIR can be the inputs of the performer ALU, but such a configuration is not only used for the microinstruction check of the present invention.

That is, in general, a processor connected to a bus has a register connected to the bus for exchanging information or data, and the register is connected to the arithmetic unit in order to process the information or data. The input U and the processor are usually equipped with a function to perform operations between the register output or the output of the register file that stores the performance output and the constant, but the constant is a part of the microinstruction. For this reason, part of the output of the microinstruction register is generated using ty 30. This is a device input.

In this way, the configuration of the present invention can be realized by simply using the general configuration of a bus-connected processor and adding some hardware to it that allows all bits of the microinstruction register to be input to the arithmetic unit. It is.

Now, a microprogram stored in an external storage medium (not shown) is output to the main memory MM at the time of system initialization, and is stored in the control memory C8 according to instructions from the processor U2 as follows. loaded.

FIG. 2 is a time chart when the microprogram is loaded. It is assumed that processors U1 and U2 operate in response to the same clock CLK. The processor U2 may or may not be operated by a microprogram control method like the processor U1.

Processor υ2, as shown in FIG.
As D, 11'ET, CH, NOP, LOAD, C3
WRITE, NOP, and AD INC are output in synchronization with the repetition clock CLK for each microinstruction in this manner. Decoder DEC decodes this command CMD and outputs a code to register REG, address generation circuit ADG, or control memory CS in accordance with the decoding result.

First, in the FETC) I cycle, the command CM
D is validated in the main memory MM, and the microinstructions of the microprogram that have already been loaded from the external storage medium are read out onto the bus BUS. Further, the address generation circuit ADD is the address At of the control meter +11cs.
- Output the specified address signal AD8. FETC)
The NOP cycle following the first cycle is a non-operation cycle provided to wait for the edict or output operation of a microinstruction from the main memory MM to the bus BU8.

In the LOAD cycle, the decoder DEC outputs a signal to the register REG, instructing it to load the microinstruction that has already been read onto the bus BU19. In the next 08 WRITE cycle to register REG, this microinstruction is actually input to register EGK@.

In response to command 08 WRITE, Deyoda DEC
instructs the control memory C8 to write the microinstruction provided by the register HG. The address of controller @CS where the write operation is performed at this time is A specified by address signal AD8 from address generation circuit ADG. The <Nov cycle following the C8 WRITE cycle is a cycle provided to wait for the contents written to the control memory C8 to be taken into the microinstruction register MI)l.

In the AD INC cycle, address generation circuit A
DD performs an operation of incrementing the previous address A in the control memory C8. Also, the above microinstruction already written in the control memory C8 is stored in the microinstruction register MIJ.
c3 is protruding.

The parity check circuit PC has a microinstruction register M
A parity check is performed on the content (A) of address A of control memory C8, which is the content of IR [MIR].

As a result of this parity check, unless a parity error is detected, the parity generation circuit PE does not output the parity error signal BS, and the performance type designation signal A
s is determined only by the microinstruction held in the microinstruction register MIH.

As mentioned above, the commands FETCH, NOP, LOAD
.

When a command cycle consisting of O8 WRITE, NOP and AD INC is completed, the next command cycle, also consisting of the same command, begins. 1b, AD I which is the last command in the previous command cycle
Nc K! <Command becomes FBTCH which is the first command in the next command cycle. Then, in the next command cycle, the same operation as in the previous command cycle is repeated.

In the FETCH cycle, as a result of the step operation for address A as described above in the previous AI) INC cycle, address signal AD8 designating address A+1 is sent from address generation circuit ADG to controller #08.
is output to. Therefore, in the continuation (NOP cycle), the memory contents held at address A+1 of control memory C8 are read into the microinstruction register MIR, but this is undefined since 1 has not yet been written to address A+1.

The waveforms of the contents of register REG (REG) and the contents of microinstruction register MIR (MIR) in FIG.
This is when the parity error signal ES is not output.

On the other hand, according to the result of the parity check in the previous AI) INC cycle, the parity check circuit PC detects a parity error, and the parity error generation circuit PE generates a parity error signal E8 (shown by a dotted line in FIG. 2).
I will explain the case. Switchers MX1 and MX2 each switch the contents held in the microinstruction register MIB [MIR
] and changes to accept the contents held in the register EG (BEG). The arithmetic control circuit ALC outputs a performance type designation signal As instructing an exclusive OR operation to the arithmetic unit ALU.

Based on the above results, the arithmetic unit ALU performs an exclusive OR operation on the contents of the microinstruction register MIR (MIR) and the contents of the register REG ()LEG) in the FBTCH cycle. By the way, in this FBTCH cycle, as mentioned above, the microinstruction register M
Since IR and register REG should originally hold the memory contents (A) of the same address A in control memory C8, when a parity error occurs, an error is caused by the result of the exclusive OR operation of the two. 3. The result of the exclusive OR operation, which determines which bits have been selected, is held in the register file RFK and can also be taken out onto the bus BUS via the buffer circuit BF, and becomes legal information for parity processing.

The parity error signal E8 is also input to the update stop circuit 1llIDT, and the update stop circuit L)T is connected to the NOP cycle in the microinstruction register MIR and the register REG.
This prevents each retained content from changing in the CB WRITE cycle. In this manner, the contents (MIR) and (REG) held in the register MI and the register REG after freezing the microinstruction can be useful information for processing the parity 2-.

However, it goes without saying that the update stop circuit jJT does not fire and is not an essential part of 8A. Furthermore, there may be two or more processors that operate according to the microprogram 21 control method, such as the processor Ul shown in FIG. .

〔Effect of the invention〕

According to the present invention, by using the above-described configuration, in the past, only the memory address of one control unit that caused a parity error and the fact that a parity error occurred, can be determined. Since even the bits can be determined, decisive information for parity error handling can be obtained with only a small amount of hardware addition1.

[Brief explanation of the drawing]

FIG. 1 shows an embodiment of the present invention, and FIG. 2 shows a time chart on the Torao side. Lll, U2... Processor, MM...
・Main memo IJ, BLI8...Bus, DEC
・・・・・・Decoder, ADG・・・−・Address generation circuit, REG・・・Register, C8・・・・・・
・Control memory, MIR...Micro instruction register, PC...Parity check circuit, PE...
... Parity era circuit regeneration, ALC ... Arithmetic control circuit, ALU ... Enabler, MXl, MX
2...Passion machine, RF...Register file, L) T...Update stop time, BP...
...Buffer circuit.

Claims (1)

[Scope of Claims] In a microprogram load check method when a microprogram with parity is loaded into one of a plurality of processors connected by a bus according to an instruction from another processor, for each processor of the microprogram control method, the bus a register that holds data input to the processor from the register; a control memory in which the microprogram is written in units of microinstructions via the register; and a microinstruction that holds microinstructions read from the control memory each time the microprogram is written. a register 1; a parity check circuit that performs a parity check when the microinstruction is input to the microinstruction register; and a parity check circuit that performs a parity check when the microinstruction is input to the microinstruction register; and a parity check circuit that each of the register and the microinstruction register holds when a parity error is detected as a result of the parity check. An arithmetic circuit 3 is provided to perform an exclusive OR operation on microinstructions, and the register and the microinstruction register hold microinstructions corresponding to the same microinstruction step until the exclusive OR operation is performed. A microprogram load check method, characterized in that the load instruction is given as follows.