JPH05189231A - Error processing system in instruction fetch - Google Patents

Abstract

PURPOSE:To provide an error processing system in instruction fetch which can simplify an error processing at the time of fetching an instruction in a micro program control system and which can simplify the constitution of hardware. CONSTITUTION:When an error occurs in instruction fetch, an error cause is set in a status 2. An undefined instruction code generation means 3 generates a prescribed undefined instruction code when the error cause is set in the status 2, and gives it to a control storage part 4. It calls an error processing program with the undefined instruction code which the undefined instruction code generation means 3 generates as an address, and executes the error processing. A micro address generation processing for a micro interruption processing becomes unnecessary with such constitution, and the error processing can easily be executed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a micro program control system computer system, and more particularly to an error processing system at the time of instruction fetch in the micro program control system.

[0002]

2. Description of the Related Art FIG. 5 is a diagram showing an error processing method in a conventional instruction fetch. In the figure, 101 is a memory management unit (hereinafter abbreviated as MMU), 102
Is a main storage device, 103 is an instruction buffer, 103a is an operation code buffer (hereinafter abbreviated as OP code buffer), 103b is a status buffer, 104 is a control storage unit, 105 is a micro program counter, 106 Is a micro instruction register, 107
Is a multiplexer (hereinafter abbreviated as MPX), 10
Reference numeral 8 is a micro interrupt circuit.

In FIG. 1, a logical address IA (INSTRU
The address indicated by (CTION ADDRES) is converted into a real address in the MMU 101, and the instruction corresponding to the address is read from the main storage device 102 and stored in the OP code buffer 103a of the instruction buffer 103. The operation code (hereinafter abbreviated as OP code) stored in the OP code buffer 103a of the instruction buffer 103 is given to the control storage unit 104 via the MPX 107, and the OP code is used as an address of the control storage unit 104 for microinstruction. Is read.

The read microinstruction is applied to the microinstruction register 106 to perform microprogram control. In addition, when the micro instruction is executed, the micro program counter 105 controls the control storage unit 10.
1 is added to the address of 4 and is given to the control storage unit 104 via the MPX, and the next micro instruction is read. Here, when an instruction is read from the main memory 102 and stored in the instruction buffer 103, if an error occurs, the error factor is set in the status buffer 103b of the instruction buffer 103. The micro interrupt circuit 108
When the error factor is set in the buffer 103b, a microinstruction address of an error processing routine corresponding to the error factor is generated, and the control storage unit 10 is transmitted via the MPX 107.
4, the microinstruction for error processing is read and error processing is performed.

By the way, in the above-mentioned conventional error processing method, when an error occurs, a process for generating a micro instruction storage address for error processing and a micro interrupt process are required, and the process when an error occurs is complicated. At the same time, there is a drawback that the hardware configuration becomes complicated.

[0006]

SUMMARY OF THE INVENTION The present invention has been made in order to improve the above-mentioned drawbacks of the conventional method, and simplifies the error processing at the time of instruction fetch in the micro program control method, and for that purpose, hard·
An object of the present invention is to provide an error handling method in instruction fetch that can simplify the hardware configuration.

[0007]

1 and 2 are block diagrams of the principle of the present invention. The invention of claim 1 of the present invention is
As shown in FIG. 1, an instruction read from the main storage unit is stored in the instruction buffer 1, and a micro instruction is read from the control storage unit 4 using the operation code stored in the instruction buffer 1 as an address to execute a micro process. In the error processing method in the instruction fetch of the control method, the undefined instruction code generating means 3 for generating a predetermined undefined instruction code when an error occurs in the instruction fetch and an error factor is set in the status 2 of the instruction buffer 1. Set up.

When an error occurs in the instruction fetch and the error factor is set in the status 2, the undefined instruction code generating means 3 generates the undefined instruction code. The control storage unit 4 calls the error processing program by using the undefined instruction code generated by the undefined instruction code generation means 3 as an address and performs error processing. According to a second aspect of the present invention, in the first aspect of the present invention, an undefined instruction code detecting means 5 for detecting that the undefined instruction code is stored in the instruction buffer 1 is provided.

Then, when the undefined instruction code detection means 5 detects an undefined instruction code, the undefined instruction code generation means 3 generates a second predetermined undefined instruction code, and the undefined instruction code generation means. A predetermined processing program is called from the control storage unit 4 and executed by using the second undefined instruction code output by 3 as an address. According to a third aspect of the present invention, as shown in FIG. 2, the instruction read from the main storage unit is stored in the instruction buffer 1, and the operation code stored in the instruction buffer 1 is used as an address from the control storage unit 4. In the error processing method in the instruction fetch of the micro control method for reading the micro instruction and executing the micro processing, an output signal of status 2 in which an error factor is set when an error occurs in the instruction fetch is given to the control storage unit 4.

When an error occurs in the instruction fetch, the error processing program of the control storage unit 4 is called based on the output signal of the status 2 and the error processing is performed.

[0011]

In the invention of claim 1 of FIG. 1, when an error occurs in the instruction fetch, the error factor is set in the status 2. When the error factor is set in the status 2, the undefined instruction code generating means 3 generates a predetermined undefined instruction code and gives it to the control storage unit 4. The control storage unit 4 calls the error processing program by using the undefined instruction code generated by the undefined instruction code generation means 3 as an address and performs error processing.

According to the first aspect of the invention shown in FIG. 1, the micro address generation process for performing the micro interrupt process is unnecessary, and the error process can be simplified. Further, since the error processing address of the control storage unit 14 is made to correspond to the unused code (undefined instruction code) of the OP code, it is not necessary to provide an additional address line for error processing, and the hardware The configuration can be simplified.

Further, as in the invention of claim 2, the undefined instruction code detecting section 5 is provided, and when the undefined instruction code is detected, the second undefined instruction code is generated and the corresponding processing is executed. With the configuration, when the undefined instruction code generation unit 3 generates an undefined instruction code due to an error, and when the instruction buffer 1 runs due to a program runaway or the like.
Can output the undefined instruction code.

According to the invention of claim 3 of FIG. 2, when the error occurs in the instruction fetch, the output signal of the status 2 in which the error factor is set is given to the control storage unit 4 to perform the error processing. The micro address generation process for performing the micro interrupt process is unnecessary, and the error process can be simplified.

[0015]

FIG. 3 is a diagram showing a first embodiment of the present invention. In the figure, 11 is an MMU, 12 is a main memory,
13 is an instruction buffer, 13a is an OP code buffer,
13b is a status buffer, 14 is a control storage unit, 1
Reference numeral 5 is a micro program counter, 16 is a micro instruction register, 17 is MPX, 18 is an undefined instruction code detector, and 19 is an undefined instruction code generator.

3 is different from the conventional example of FIG. 5 in that the micro interrupt circuit 108 is removed, and an undefined instruction code detection section 18 and an undefined instruction code generation section 19 are added. Has a configuration similar to that of FIG.
The undefined instruction code detector 18 in FIG. 3 is means for detecting the case where the OP code read from the OP code buffer 13a is an undefined instruction code. here,
The undefined instruction code means a code that is not defined as an OP code, that is, a code that is not used as an OP code, and usually occurs, for example, when a program runs out of control.

The undefined instruction code generation unit 19 detects an undefined instruction code when an error occurs and the error factor is set in the status buffer 13b of the instruction buffer 13. In this case, the means for generating the first and second predetermined undefined instruction code signals respectively, and when no error occurs or the undefined instruction code is not detected, the OP code buffer 13a OP read
The code is given as it is to the control storage unit 14 via the MPX 17.

An error processing program is stored in the control storage unit 14 of FIG. 3 at an address corresponding to the first predetermined undefined instruction code. In addition, the control storage unit 1
A processing program at the time of detecting an undefined instruction code is stored in the address of No. 4 corresponding to the second predetermined undefined instruction code. For example, an undefined instruction code that is composed of 8 bits and is not defined as an OP code is {'03', '80', 'FF'} in hexadecimal notation.
When there are three types of undefined instruction codes, {'FF'} is assigned to the error processing. Then, when an error occurs and the error factor is set in the status buffer 13b of the instruction buffer 13, the undefined instruction code generator 19 generates the undefined instruction code {'FF'}.

When the undefined instruction code detector 18 detects an undefined instruction code, the undefined instruction code generator 19 generates {'80'} among the undefined instruction codes. On the other hand, the address of control storage unit 14 {'FF'}
Stores an error processing program, and the undefined instruction code generation unit 19 causes the undefined instruction code {'F
When F '} is generated, the error processing program at the address {' FF '} is called and executed. Further, a processing program at the time of detecting an undefined instruction code is stored in the address {'80'} of the control storage unit 14, and the undefined instruction code generation unit 19 generates the undefined instruction code {'80'}. Then, the processing program at the address {'80'} is called and executed.

Next, the operation of the embodiment shown in FIG. 3 will be described. If no error has occurred when fetching the instruction, the logical address IA is used as in the conventional example shown in FIG.
The address indicated by (INSTRUCTION ADDRES) is converted into a real address in the MMU 11, and the instruction corresponding to the address is read from the main storage device 12 and the instruction buffer 13
Is stored in the OP code buffer 13a.

The OP code stored in the OP code buffer 13a of the instruction buffer 13 is given to the control storage unit 14 via the MPX 17, and the OP code is stored in the control storage unit 14.
The micro instruction is read as the address of. The read microinstruction is given to the microinstruction register 16 and microprogram control is performed. Also,
When a microinstruction is executed, the micro program counter 15 adds 1 to the address of the control storage unit 14 and gives it to the control storage unit 14 via MPX, and the next microinstruction is read.

Here, when an instruction is read from the main memory 12 and stored in the instruction buffer 13, when an error occurs, the error factor is set in the status buffer 13b of the instruction buffer 13. When an error factor is set in the status buffer 13b, the undefined instruction code generator 19 causes a first predetermined undefined instruction code (for example, {'F
F ′}) is generated. This undefined instruction code is MPX1
The error processing program of the address given to the control storage unit 14 via 7 and called at the address corresponding to the first undefined instruction code is called and executed.

When an undefined instruction code is set in the OP code buffer 13a of the instruction buffer 13 due to a program runaway or the like, the undefined instruction code detection unit 1
8 generates an output, and the undefined instruction code generator 19 outputs the second
A predetermined undefined instruction code (eg, {'80'}) of This undefined instruction code is given to the control storage unit 14 via the MPX 17, and the processing program of the address corresponding to the above-mentioned second undefined instruction code is called and executed.

By providing the undefined instruction code detection unit 18 and generating a second undefined instruction code when an undefined instruction code is detected and executing a process corresponding to the second undefined instruction code, an undefined instruction code is generated when an error occurs. It is possible to discriminate between the case where the instruction code generator 19 generates an undefined instruction code and the case where the undefined instruction code is output from the OP code buffer 13a due to a program runaway or the like.

In this embodiment, as described above, when an error is detected, the undefined instruction code is output to the control storage unit to perform the error processing. Therefore, the micro interrupt circuit in the conventional example is not necessary, and The micro address generation process for performing the micro interrupt process is unnecessary, and the error process can be simplified. Further, since the error processing address of the control storage unit 14 is associated with the unused code (undefined instruction code) of the OP code, error processing can be performed without providing an address line for error processing. The hardware configuration can be simplified.

In the above embodiment, the case where there is only one type of undefined instruction code output when an error occurs has been described. However, when a plurality of error factors are set in the status buffer 13b, Accordingly, a plurality of undefined instruction codes can be assigned and the processing corresponding to the error factor can be executed. FIG. 4 is a diagram showing a second embodiment of the present invention. The figure a shows a part of the configuration, and the configuration other than the part shown in the figure a has the same configuration as that shown in FIG. 3, and the same components as those in FIG. 3 are the same. Is attached. In addition, FIG.
FIG. 6 is a diagram illustrating the operation of FIG.

In this embodiment, the OP code buffer 13a is used.
In addition to the output of the status buffer 13b, the output of the status buffer 13b is added to the MPX17. For example, the OP code is 8 bits and the status buffer 1
When the output of 3b is 1 bit, as shown in FIG.
A 9-bit signal is added to the MPX 17. Then, when an error occurs at the time of instruction fetch and the error factor is set in the status buffer 13b, as shown in FIG. 4b, an error signal is sent to the first bit of the address (CS address in FIG. 4b) of the control storage unit 14. Is set.

On the other hand, an error processing program is stored in the corresponding address of the control storage unit 14, as shown in FIG.
When the error signal is set to the first bit of the CS address of, the error processing program is called and the error processing is executed. In the present embodiment, since it is configured as described above, the micro interrupt circuit in the conventional example becomes unnecessary, and the micro interrupt circuit for performing the micro interrupt processing is not required.
Address generation processing is unnecessary and error processing can be simplified.

When a plurality of error factors are set in the status buffer 13b, the number of bits of the address of the control storage unit 14 can be increased accordingly and error processing corresponding to the error factors can be performed. ..

[0030]

As is clear from the above description,
In the present invention, the micro interrupt circuit in the conventional example is not necessary, and the micro address generation process for performing the micro interrupt process is unnecessary, so that the error process can be simply performed. In particular, claim 1 of the present invention
According to the invention, since the error processing address of the control storage unit 14 is associated with the unused code (undefined instruction code) of the OP code, an extra address line for error processing is added to the control storage unit 14. Error processing can be performed without providing, and the hardware configuration can be simplified.

[Brief description of drawings]

FIG. 1 is a principle diagram of the present invention.

FIG. 2 is a principle view of the present invention.

FIG. 3 is a diagram showing a first embodiment of the present invention.

FIG. 4 is a diagram showing a second embodiment of the present invention.

FIG. 5 is a diagram showing a conventional example.

[Explanation of symbols]

 11 MMU 12 Main memory 1, 13 Instruction buffer 13a OP code buffer 13b Status buffer 4,14 Control memory 15 Micro program counter 16 Micro instruction register 17 MPX 5.18 Undefined instruction code detector 3,19 Undefined instruction code generator

Claims (3)

[Claims] 1. A micro-process in which an instruction read from a main memory is stored in an instruction buffer (1), and a micro-instruction is read from a control memory (4) using an operation code stored in the instruction buffer (1) as an address. In the error processing method of the instruction fetch of the micro control method that executes
An undefined instruction code generation means (3) that generates a predetermined undefined instruction code when an error factor is set in the status (2) of is provided, and the undefined instruction output by the undefined instruction code generation means (3) An error processing method in an instruction fetch characterized in that error processing is performed by calling an error processing program from the control storage unit (4) and executing it using a code as an address. 2. An undefined instruction code detecting means for detecting that an undefined instruction code is stored in the instruction buffer (1).
(5) is provided, and when the undefined instruction code detection means (5) detects an undefined instruction code, the undefined instruction code generation means (3) generates a second predetermined undefined instruction code, The instruction fetch error according to claim 1, wherein a predetermined processing program is called from the control storage unit (4) and executed by using the second undefined instruction code output from the defined instruction code generation means (3) as an address. Processing method. 3. The instruction read from the main memory is stored in the instruction buffer (1), and the microcode is read from the control memory (4) by using the operation code stored in the instruction buffer (1) as an address. In the error processing method for the instruction fetch of the micro control method that executes the, the output signal of the status (2), which sets the error factor when an error occurs in the instruction fetch, is given to the control storage unit (4) and When an error occurs, the error processing method in the instruction fetch is characterized in that the error processing is performed by calling and executing the error processing program of the control storage unit (4) based on the output signal of the status (2).