JPS61160149A - Data processor - Google Patents

Abstract

PURPOSE:To provide the detailed information of a parity error by detecting the error bit information of a corresponding microinstruction when the intermittent trouble of a microprogram is detected. CONSTITUTION:A data processor is provided with a control storage 1, a microinstruction register 2, a parity check circuit 3, an address generating circuit 4, an address register 5, a multiplexer 6, a flip flop 7, a control circuit 8, a switching circuit 9, a clock control circuit 10, the 1st and 2nd register files 11, and an operator 13. The operator 13 is commanded to execute exclusive OR between the outputs of the register file 111 and the multiplexer 12 and store the arithmetic result in a register file 112. Since a coincident bit is turned to '0' and a dissident bit is turned to '1', an illegal bit can be easily decided.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a data processing device using a microprogram control method.

(Prior Art) Conventionally, microprogram control type data processing devices have generally been configured so that microprograms stored in a control memory are sequentially read out and executed. On the other hand, ROM or RAM is usually used for control storage, but these memory devices are generally less reliable than other types of devices, and are subject to intermittent failures due to parity errors in microinstructions. There were many cases where this happened.

Conventionally, from this point of view, a parity bit has been added to a microprogram and stored in a control memory, and a parity check has been performed each time a microinstruction read from the control memory is executed. In such a system, when an error is detected by a parity check, an error pit is set and the microinstruction is reread and re-executed (Japanese Patent Application No. 49268/1982).

(Problems to be Solved by the Invention) However, re-reading and re-executing the microinstructions results in a loss of execution time, and furthermore, there is always the possibility that an intermittent failure will become a fixed failure. Therefore, it goes without saying that even if a normal microinstruction can be read out by rereading, it is desirable to eliminate the cause of the failure.

However, in case of intermittent failure, which pit! 14
It is extremely difficult to know whether a mistake was made, and this poses a problem in the processing of errors.

An object of the present invention is to eliminate the above-mentioned drawbacks by detecting error pit information of the corresponding microinstruction when an intermittent failure of a microprogram is detected, and to provide detailed information on parity errors. The object of the present invention is to provide a data processing device configured as follows.

(Means for Solving the Problems) A data processing device according to the present invention includes a control memory, a microinstruction register, a parity check circuit, an address generation circuit, an address register, a multiplexer, a flip-flop, and a control circuit. , a switching circuit, a clock control circuit, first and second register files,
It is configured to include a computing unit.

The control memory is for storing a microprogram including parity bits, the microinstruction register is for holding the output of the control memory, and the parity check circuit performs a parity check on the contents of the microinstruction register. The address generation circuit is used to generate a read address according to a microprogram, and the address register is used to hold the read address of the control memory.

The multiplexer is for generating a microinstruction address by inputting the output of the address register and the output of the address generation circuit.

The flip-flop converts the output of the parity check circuit into 1
It is meant to be held over a clock cycle.

The control circuit receives the output of the flip-flop and the output of the parity check circuit to generate a control signal.

The switching circuit receives the output of the control circuit and generates a switching signal for the multiplexer.

The clock control circuit is for providing clocks to the address registers, microinstruction registers, and flip-flops.

The first register file is for holding the contents of the microinstruction register when a parity error is detected.

The arithmetic unit is for performing an exclusive OR operation on the first register file and the microinstruction register in the cycle following the detection of the parity error.

The second register file is for holding the results of calculations by the arithmetic unit.

(Example) Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a data processing apparatus according to the present invention. In FIG. 1, a data processing device using a microprogram control system has a control memory 1 for storing a microprogram including parity bits.
and a microinstruction register 2 for holding the output of the control memory 1, a parity check circuit 3 for checking the microinstruction output from the microinstruction register 2, and a parity check circuit 3 for checking the output of the microinstruction register 2. N), (T), an address register 5 to hold the read address (MAR) of the control memory 1, and the next address from the address generator circuit 4 and the output of the address register 5. is input as address information, and the multiplexer 6 selects and outputs one of the address information according to the switching instruction, and the parity error signal (P
CE) for one clock cycle, a control circuit 8 consisting of an AND gate 81 and an OR gate 82 which input the parity error signal and the output of the flip-flop 6, and an AND of the control circuit 8.
A switching circuit 9 inputs the output (TRAP) of the gate 81 and the output (NOP) of the OR gate 82 and instructs the multiplexer 6 to switch, and an OR circuit inside the control circuit 8.
Inverters 101 and 105 that are controlled by the output signal (NOP) of gate 82 and NAND gate 102
a clock control circuit 10 and first and second register files 111.

A pair of register files 11 consisting of 112 and a multiplexer 12 to which the output of the second register file 112 and the contents of the microinstruction register 2 can be input.
, an arithmetic unit 13 to which the output of the multiplexer 12 and the output of the first register file 111 can be input, the output of the flip-flop 7, and the microinstruction register 2.
, and an arithmetic control circuit 14 to which the output of , as well as the NOP signal can be input. The clock control circuit 10 is N
AND gate 102 and inverter 101.

103, the C1N0P signal is inverted by the inverter 101, and the NAND gate 102 receives this inverted signal (N
OP) and the basic clock (CLK) to output a clock CLK2. The clock CLK2 is supplied to and used by other registers and flip-flops (not shown) inside the data processing device according to the present invention. Therefore, when the clock CLK2 stops, the data processing device does not operate according to the microinstruction, and the contents of the register are held as they are. A basic clock (CLK
) is supplied with an inverted clock CLK1. A parity error signal (PCB) is input to the flip-flop 7, and is set by the inverted clock CLKI.

FIG. 2 is a time chart showing the main signals of the data processing device shown in FIG. FIG. 2 shows the sequence of microinstructions and the operation of the register file 11 and the arithmetic unit 13 during a parity error. That is,
FIG. 2 shows how an intermittent parity error is detected in a microinstruction, the microinstruction is successfully reread, and the error bit information is written to the register file 112. Symbols MAR, AD, MIR, in Figure 2
NOP, TRAP, PCF, F/F, N.

P, CLKI, CLK2, and CLK each correspond to the symbols on the signal lines shown in FIG.

In FIG. 2, a, a, and b indicate microinstructions corresponding to the respective read addresses A, A, and B, especially a'!
is a microinstruction corresponding to read address A that contains a parity error. The time chart for one operation is multiplexer 12. The operations of the arithmetic unit 13 and the register files 111 and 112 during parity error are collectively displayed.

Next, the operation of this embodiment will be explained in detail with reference to FIGS. 1 and 2. In FIG. 2, part of the output of the microinstruction register 2 is input to the address generation circuit 4, and the read address signal A generated thereby is sent to the multiplexer 6.
is input. During normal operation, the parity error (No. 8 (PCE)) input to the switching circuit 9 and the output of the flip-flop 7 are both at low level. A is selected and output as a read address (MAR).The read address is the read address input of control memory 1, and when microinstruction a containing a parity error is read out and clock CLK1 rises, it is output to microinstruction register 2. read address (MAR) at the same time.
) is taken into address register 5. microinstruction a
from microinstruction register 2 to parity check circuit 3
When the parity check circuit 3 detects a parity error, the parity error signal (PCE) becomes high level. When the output of the flip-flop 7 is at a low level, the output of the OR gate 82 of the control circuit 8 is at a high level. Since the output of the AND gate 81 is at a low level, the switching circuit 9 instructs the multiplexer 6 to select and output the output of the address register 5, so that the read address (MAR) becomes A again. Since the output signal (NOP) of the OR gate 82 is at a high level, the NOP signal is inverted by the inverter 101 inside the clock control circuit 10, inputted to the NAND gate 102, and gated by the clock CLK. At this time, the output CLK2 of the NAND gate 102 is kept at a high level, so the clock is stopped. Furthermore, the NOP signal is input to the arithmetic control circuit 14. When the NOP signal is at a high level, the arithmetic control circuit 14 instructs the multiplexer 12 to select and output the output of the microinstruction register 2.

On the other hand, when the NOP signal is at a high level and the output of the flip-flop 7 is at a low level, the arithmetic unit 13 is instructed to select the output of the multiplexer 12, and the register file 111 is instructed to select the output of the arithmetic unit 15. Instructs to capture output. That is, the output a of the microinstruction register 2 is taken into the register file 111.

Next, since the parity error signal (PCB) is at a high level, the flip-flop 7 takes in the parity error signal (PCE) at the rising edge of the next clock after the microinstruction register 2 takes in the microinstruction a. The output of flip-flop 7 becomes high level. At the same time, the normal microinstruction a reread by the read address A is taken into the microinstruction register 2, and %AI is taken into the address register 5. Since microinstruction a is normal, the parity error signal (PCE) becomes low level. At this time, since the output of the flip-flop 7 is at a high level, the NOP signal becomes a high level, and the output signal TRAP of the AND gate 81 becomes a low level. The switching circuit 9 sends an instruction to the multiplexer 6 to select and output the address register 5 again. At this time, %A' is output to the read address. Since the NOP signal is at a high level, the clock CLK2 is at a high level! There is even. Since the signal NOP is at a high level, the arithmetic control circuit 14 instructs the multiplexer 12 to select and output the microinstruction register 2. At this time, since NOP is at a high level and the output of flip-flop 7 is at a high level,
The register file 111 is instructed to read the microinstruction a written in the previous cycle from the register file 111 and output it. Furthermore, for the arithmetic unit 13, a register file 111 and a multiplexer 12 are provided.
It instructs to perform an exclusive OR operation with the output of , and instructs to store the result of the operation in the register file 112.

At this time, since the normal microinstruction a is stored in the microinstruction register 2, if the exclusive OR of microinstruction a and microinstruction a is executed, the matched bit will be %OI, but Since %11 is set for the mismatched bit, it is easy to determine which bit is incorrect. The information stored in the register file 112 is later retrieved by instructions from a host device, but this method is not related to the present invention and will therefore be omitted.

Since address A is advanced to the read address (MAR), microinstruction a is read out again and taken into microinstruction register 2 in the next cycle. FIG. 2 shows the microinstruction register 2 executing the microinstruction %al for the second time. At this time, the parity error signal (PCE) is at a low level, and the flip-flop 7
Since the output of is also at a low level, the NOP signal is also at a low level. Also, since the TRAP signal is also low level, the NA
ND gate 102 outputs CLK2 and microinstruction a
is executed. At this time, the switching circuit 9 selects the address generating circuit 4 and instructs it to output. Microinstruction B generated by address generation circuit 4 is selected and output, the read address (MAR) becomes microinstruction B, and execution of the next instruction begins.

In the present invention, the microinstruction register 2 is replaced by the arithmetic unit 13.
A multiplexer 12 is provided to input the
Normally, a function is provided to perform an operation between the output of the register file 11 that stores the operation output and a constant. The above constants are generated using part of the microinstruction, and part of the microinstruction register serves as an input to the arithmetic unit. As described above, the present invention is realized by using the general configuration of a data processing device and adding some hardware to it, and it is possible to easily remove pits where errors occur due to intermittent failures due to parity errors. This provides crucial information for error handling.

(Effects of the Invention) As described above, the present invention, when an intermittent failure of a microprogram is detected, detects the erroneous sibit information of the corresponding microinstruction, thereby making it possible to provide detailed information on the parity error. This has the effect of improving reliability.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a data processing apparatus according to the present invention. FIG. 2 is a time chart showing waveforms of various parts of the data processing device shown in FIG. 1. Microinstruction register 5 of fist φ control memory 2... Parity check circuit 4... Address generation circuit 5... Atsis register, 12. Φ. Multiplexer 1.・-Control circuit 9...Switching circuit 10...φ clock control circuit 11.111.112・e・Register file 13...
- Arithmetic unit 14...arithmetic control circuit

Claims (1)

[Claims] A control memory for storing a microprogram including parity bits, a microinstruction register for holding the output of the control memory, and a parity check circuit for performing a parity check on the contents of the microinstruction register. , an address generation circuit for generating a read address according to a microprogram, an address register for holding a read address of the control memory, and an output of the address register and an output of the address generation circuit are input. a multiplexer for generating a microinstruction address; a flip-flop for holding the output of the parity check circuit for one clock cycle; and inputting the output of the flip-flop and the output of the parity check circuit. a control circuit for generating a control signal; a switching circuit for inputting the output of the control circuit to generate a switching signal for the multiplexer; and supplying a clock to the address register, the microinstruction register, and the flip-flop. a first register file for holding the contents of the microinstruction register when the parity error is detected; and a first register file for holding the contents of the microinstruction register when the parity error is detected; A register file and an arithmetic unit for executing an exclusive OR operation on the microinstruction register, and a second register file for holding the result of the operation by the arithmetic unit. Data processing equipment.