JPS59173849A - Data processing device - Google Patents

Abstract

PURPOSE:To enable reading of microinstruction even when a parity error occurs by switching output of a register that holds control memory reading address and output of an address generating circuit by output of a parity check circuit. CONSTITUTION:An address register 5 holds control memory reading address. The output and output of an address generating circuit 4 are inputted to a multiplexer 8. The multiplexer 8 is switched by output of a parity check circuit 3 and the output is inputted to a control memory circuit 1. A microinstruction register 2 holds output of the control memory circuit 1, and the output is parity checked by the parity check circuit 3. A counter 6 counts the parity error signal, and when the counting value arrives at a fixed value, outputs a counter output signal. A clock controlling circuit 9 is controlled by the parity error signal and outputs specified clock signal.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data processing device, and more particularly to a microprogram-controlled data processing device.

In general, it is an extremely important requirement from the viewpoint of improving the reliability of the data processing device that data processing using a microprogram control method be executed reliably.

Conventionally, from this point of view, a parity pit is added to a microprogram and stored in a control storage circuit, and a parity check is performed each time the microprogram read from the control storage circuit is executed, and an error is detected as a result of the parity check. When an error occurs, a beep indicating the occurrence of an error is set in the Va register to report this to the host device, or the system operation is halted. However, in which method, when a parity error in a microinstruction is detected, the currently executing microinstruction
” Since the o-gram has to be aborted, it greatly hinders the progress of system operation, and the results of the execution up to that point are often wasted. On the other hand, the control memory circuit usually has ROM or RAM is used, but these memory devices are generally less reliable than other devices and are prone to microinstruction parity errors, and their failures are intermittent. There were also quite a few drawbacks.

An object of the present invention is to eliminate the above-mentioned drawbacks by adding a small-scale hardware, and to provide high reliability in which even if a microinstruction parity error occurs, the microinstruction can be reread and reexecuted. The object of the present invention is to provide a microprogram-controlled data processing device.

A data processing device according to the present invention includes a control storage circuit that stores a microprogram including parity pits, a first register that holds an output direction of the control storage circuit, and a parity check that performs a parity check of the output of the first register. A microprogram control type data processing device comprising a circuit and an address generation circuit that generates a read address according to a microprogram, a second register that holds a control memory read address, an output of the second register, and the address generation circuit. The present invention is characterized in that it includes a multiplexer that receives a circuit output signal as an input, and a switching circuit that instructs the multiplexer to switch based on the output of the parity check circuit.

Further, a clock control circuit controlled by the output of the parity check circuit is added to this data processing device, and the clock control circuit is operated by the output of the clock control circuit, and furthermore, the parity check circuit detects a counter that counts the number of parity errors made and outputs a signal when the count value reaches a predetermined value, and includes specific address information at the input of the multiplexer and the counter output signal at the input of the switching circuit. It is characterized by

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a data processing device of the present invention. In the figure, a microprogram control type data processing device includes a control storage circuit (hereinafter referred to as C3) l that stores a microprogram including valid pits,
A microinstruction register (hereinafter MIR) 2 that holds the output of the C8I and a microinstruction register (hereinafter MIR) 2 that holds the output of the C8I and a microinstruction register (hereinafter MIR) 2 that holds the output of the C8I.
A parity check circuit (hereinafter referred to as pc) 3 that performs a measurement check of I), and an address generator that generates a read address (next address, hereinafter referred to as NXT) according to the control of the micro valve Φ- of the MIR2 control 4-b= section. Circuit (hereinafter referred to as AD8) 4
, a γ address register (hereinafter referred to as ADR) 5 that holds the read address (hereinafter referred to as MAR) of the contents of said C8l, and said P
A 4-bit counter (hereinafter referred to as CNT) 6 that counts the parity error signal (hereinafter referred to as PCB) output from the CB and outputs a counter output signal (hereinafter referred to as CT) when the count value reaches a predetermined value; a switching circuit (hereinafter referred to as 5EL) 7 which inputs and instructs a multiplexer (hereinafter referred to as MPX) 8 to switch according to the input conditions; and the ADS 5.
Input the NXT from the ADR 4, the read address (hereinafter referred to as AD) from the ADR 4, and specific address information from the outside (for example, a trap address (hereinafter referred to as TRP)), and select one of these address information according to the switching instruction. The clock control circuit (hereinafter referred to as CLC) 9 is controlled by the PCB and outputs a predetermined clock signal CLK2. In addition, the CLC
9 consists of an inverter (hereinafter referred to as Nv) 90 and a NAND gate (hereinafter referred to as G) 91, the INV90 inputs the PCE and outputs an inverted signal PCB, and the G91 inputs the inverted signal PCB and a basic clock signal from the outside. (hereinafter referred to as CLK)
are NANDed and the clock signal CLK2 is output. The clock signal CLK2 is applied to other registers and flip-flops (both not shown) in this data processing device.
Used as a clock for data and signal acquisition. Therefore, if the clock signal CLK2 stops,
The data processing device does not operate according to microinstructions,
The contents of the registers and the like will be held. Further, an inverted clock signal CLK1 of the CLK is applied to each clock terminal CP of the MIR2, ADR5, and CNT6 via INVIO, and the contents of the register are held every cycle of the CLK. Therefore, the clock signals CLK□ and CLK2 are synchronous and in-phase clock signals. Further, the load mode terminal LD and counter mode terminal BP of the CNT6 are connected directly and INVI, respectively.
The PCB is branched and supplied via I, and the fixed value setting terminal is set to a predetermined value (for example, 1101" or "D').

The difference between this embodiment and the conventional data processing device is ADR5,
CNT6.8EL7 and MPX8 are added, and both of these circuits can be easily realized using conventional technology.

Next, FIGS. 2, 3, and 4 are time charts showing the main signals and microinstruction sequences in step 1-1, respectively. Figures 3 and 4 respectively show a time chart when the rereading of the microinstruction is successful during an abnormality (that is, when the above parity error occurs) and when the rereading fails and is trapped. The time chart is shown below.

In the same figure, reference symbols MAR, MI, AD, P
C.E.

CT, CNT, CLK, CLK2 and CI respectively correspond to those shown in FIG. shows. Also reference sign a/
, b/ , C/ , d/ , e/ , fl
, x/, y/ are read addresses aI b, respectively.
l' l d l el f Indicates the microinstruction corresponding to 1x,y. Note that the reference numeral ♂ in FIGS. 3 and 4 indicates a microinstruction corresponding to the emerging address C, which includes a error.

EF and 0 are the output values of CNT6 (shown in Figure 1),
They represent hexadecimal numbers D", E", F" and 0", respectively.

Next, the operation of this embodiment will be explained in detail.

First, in FIG. 1, NXT generated by inputting a part of MI output from MIR2 to ADS4 is inputted to MPX8. During normal operation, the PCB and CT input to 5EL7 are both low 1'L'', so the MPX8 selects the NXT based on the instruction from the 5RL7 and outputs MAR.
Output as .

The MAR is the read address input of C81, and changes every cycle so that MIa', ~f' (shown in FIG. 2) corresponding to MARa, ~f (shown in FIG. 2) is the clock signal C.
At the rising edge of LK1 (shown in FIG. 2), the data is sequentially input to MIR2 and executed.

Note that the MAR is set to ADR5 at the rising edge of the CLK□.
Therefore, the MAR is held in the ADR5 with a delay of one cycle (indicated in FIG. 2 by reference numeral IT).

Next, the abnormal operation is MARa,b as shown in Figure 3.
After the corresponding MIa' and b' are sequentially fetched into the MIR2 and executed, the MI♂ corresponding to MARc is transferred to the MI
At the same time, the M A Rc is taken into the AD
Incorporated into R5. When the MId/ is input from the MIR2 to the PCB (shown in FIG. 1) and the PCB detects a parity error, the PGE1 is high, and the output OCT of HICCNT6 (shown in FIG. 1) is low. J So, according to the instruction from the 8EL7, the MPX8 selectively outputs the AD from the ADR5, so the output becomes MARc again.
MIc' corresponding to ARc is reread and taken into the MIR2. On the other hand, the PCE goes high (fi/)
When the inverted signal PC of INV90 (shown in Figure 1) outputs
B is input to 091 (shown in Figure 1), and G91 is input to C
The output clock signal CLK is output by LK.
Since the clock signal 2 is kept high, the clock is stopped. Then, the M I c' is taken into the MIR2, and since no parity error of the M I c' is detected (the M I c' is a normal microinstruction), the P
CB becomes low “L”, and the MPX8 becomes the 5EL7.
According to the instruction, NXT is selected and MARd is output. On the other hand, the input signal to the G90 is inverted and the clock signal C
LK2 will now occur again. While the above CLK2 is stopped at high "H", the contents of other registers and flip-flops in the data processing device do not change as described above. Therefore, the effect of effectively invalidating the execution of the above MId' is There is. Note that when the PC·E becomes high ``H'', the counter mode terminal EP becomes low ``L'' in the CNT6.
At ``, the load mode terminals I and D go high and start counting, and the count is increased from a certain fixed value ``D'' to E'', but a normal microinstruction is read out at the next reread. , the PCE becomes i-L", so the fixed value "D" is loaded again. The count value of the CT is O”
Only when the signal is high, ``'H'', and when the signal is ``E'', there is a low level t, so that normal operation is performed. That is, MI d', e', and f' are sequentially read and executed.

Here, if a state in which a normal microinstruction is not read out even if re-reading continues (that is, when a fixed error occurs), the read address remains MARc and an endless loop occurs. To prevent this, if the microinstruction cannot be read normally even after repeating the rereading operation a predetermined number of times, it is determined that microprogram processing is impossible, and the presence or absence of a failure is reported to the host device. is desirable. The operation of this embodiment in such a case will be explained. Fourth
In the figure, as described above, the CNT 6 counts up every time the clock signal CLK rises when the PCB is high. The CNT6 has a fixed value "D"
” is loaded, so the count value is “D”-E“-F
It progresses as "-O", and when it finally reaches 0 in the third counting operation, the output OCT becomes high "H".The 8EL7 mentioned above
gives an instruction to the MPX8 under the condition that this CT is high ``H'', and the MPX8 is given a specific address and information. Subsequently, MIy/ corresponding to MARy is read out and executed in the same manner. That is, when a fixed error occurs in a microinstruction, a microprogram processing operation is performed to deal with the error.

Although this embodiment shows the case where a fixed error occurs in MIc, it goes without saying that the same operation will be performed even if a fixed error occurs in other microinstructions. In addition, when the microinstruction corresponding to the same read address is fetched into the microinstruction register four times in a row, and the rereading is repeated three times, the trap processing is started. It doesn't have to be limited. In other words, an arbitrary number of times can be set simply by changing the fixed value loaded into the counter.

As is clear from the above explanation, according to the data processing device of the present invention, even if a parity error of a microinstruction occurs due to the addition of small-scale hardware, the microprogram stored in the control storage circuit can It is possible to re-read and re-execute the cycle, and by stopping the clock, it is possible to invalidate the microinstruction in the cycle that caused the parity error, which has the effect of significantly improving system reliability. .

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the data processing device of the present invention, and FIGS. 2, 3, and 4 are time charts showing the main signals and microinstruction sequences in FIG. 1, respectively. . In the figure, 1... control storage circuit C'S, 2...
Old... Micro instruction register MIR, 3... Parity check circuit PC, 4... Address generation circuit AD S15... Address register ADR
, 6...4-bit counter CNT, 7...
...Switching circuit SEL, 8...Multiplexer M
PX, 9... Clock control circuit CLC, 10,
11,90...A Inverter INV. 91...Nant Gate G0 Agent Patent Attorney Susumu Uchihara

Claims (1)

[Claims] (1) A microprogram including a parity pit.
A control memory circuit for storing a control memory circuit, a first register for holding an output of the control memory circuit, a parity check circuit for performing a parity check of the output of the first register, and an address generation circuit for generating a read address according to a microprogram. In a microprogram control type data processing device comprising: a second memory for holding a control memory read address;
a register, a multiplexer which receives the output of the second register and the output of the address generation circuit, and a switching instruction is given to the multiplexer by the output of the security check circuit (2, Claim No. 1) 2. The data processing device according to item 1, wherein a clock control circuit controlled by the output of the parity check circuit is added, and the data processing device is operated by the output of the clock control circuit. 3) In the data processing device according to claims (1) and (2), the parity check circuit counts the number of barity errors detected, and when the count value reaches a predetermined value, a signal is emitted. What is claimed is: 1. A data processing device comprising: a counter for outputting a counter; an input of a multiplexer includes specific address information; and an input of a switching circuit includes the counter output signal.