JPS5525119A - Microprogram controller - Google Patents

Microprogram controller

Info

Publication number
JPS5525119A
JPS5525119A JP9720278A JP9720278A JPS5525119A JP S5525119 A JPS5525119 A JP S5525119A JP 9720278 A JP9720278 A JP 9720278A JP 9720278 A JP9720278 A JP 9720278A JP S5525119 A JPS5525119 A JP S5525119A
Authority
JP
Japan
Prior art keywords
microinstruction
register
address
error
microprogram
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9720278A
Other languages
Japanese (ja)
Inventor
Kunio Matsuoka
Hideo Yamamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP9720278A priority Critical patent/JPS5525119A/en
Publication of JPS5525119A publication Critical patent/JPS5525119A/en
Pending legal-status Critical Current

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  • Debugging And Monitoring (AREA)

Abstract

PURPOSE: To extract instructions from a provied register, where microinstructions stand by in the execution of a microprogram, when an error occurs and then to reexecute them.
CONSTITUTION: Microinstruction addresses in address register 1 are supplied to stand-by register 4 via signal line 3; corresponding microinstruction data from cotrol memory 5, on the other hand, are set to microinstruction register 6 where check 11 on an error is made, and when no error is found, they are decoded 12, thereby performing fixed logical operation. If an error is detected through check 11, timing stop 14 is made and the execution of microorder 13 is stopped; and microinstruction address generating circuit start signal 15 is sent to microinstruction address of a microinstruction data correction microprogram is sent to register 1, so that instructions in the address in method 4 having recovered will be reexecuted on the basis of the initial address.
COPYRIGHT: (C)1980,JPO&Japio
JP9720278A 1978-08-11 1978-08-11 Microprogram controller Pending JPS5525119A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9720278A JPS5525119A (en) 1978-08-11 1978-08-11 Microprogram controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9720278A JPS5525119A (en) 1978-08-11 1978-08-11 Microprogram controller

Publications (1)

Publication Number Publication Date
JPS5525119A true JPS5525119A (en) 1980-02-22

Family

ID=14186014

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9720278A Pending JPS5525119A (en) 1978-08-11 1978-08-11 Microprogram controller

Country Status (1)

Country Link
JP (1) JPS5525119A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5968060A (en) * 1982-10-13 1984-04-17 Hitachi Ltd Retrial system of control memory
JPS59173849A (en) * 1983-03-24 1984-10-02 Nec Corp Data processing device
JPS6178196U (en) * 1984-10-29 1986-05-26

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5968060A (en) * 1982-10-13 1984-04-17 Hitachi Ltd Retrial system of control memory
JPS59173849A (en) * 1983-03-24 1984-10-02 Nec Corp Data processing device
JPS6178196U (en) * 1984-10-29 1986-05-26

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