JPS5530786A - Microprogram control device - Google Patents

Microprogram control device

Info

Publication number
JPS5530786A
JPS5530786A JP10390278A JP10390278A JPS5530786A JP S5530786 A JPS5530786 A JP S5530786A JP 10390278 A JP10390278 A JP 10390278A JP 10390278 A JP10390278 A JP 10390278A JP S5530786 A JPS5530786 A JP S5530786A
Authority
JP
Japan
Prior art keywords
register
microinstruction
circuit
operated
generated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10390278A
Other languages
Japanese (ja)
Inventor
Kazuo Yasue
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP10390278A priority Critical patent/JPS5530786A/en
Publication of JPS5530786A publication Critical patent/JPS5530786A/en
Pending legal-status Critical Current

Links

Landscapes

  • Techniques For Improving Reliability Of Storages (AREA)
  • Debugging And Monitoring (AREA)

Abstract

PURPOSE: Not only to simplify the hardware constitution but also to make it possible to ged rid of wrong operation of microinstruction itself, by checking all the contents of the memory by scanning for a given period of time before the microinstruction is executed.
CONSTITUTION: When the inital setting signal INIT is provided to the signal line 14, the address register 2 and the microinstruction register 3 are cleared to "0" in the state that the parity has been generated, and also FF 7 and 8 are set to output "0", therefore the microinstruction execution circuit is not operated, and as matter of course, no error is detected by the parity check circuit 5. Subsequently, when the first clock pulse CP is generated in the signal line 12, the register 2 becomes "1" by the sequencer, the contents of address "0" are set in the register 3, and the parity check 5 is executed. In this case, since FF8 is "0", the circuit 6 is not operated, and after that, the foregoing status is continued whenever CP is generated, but when the register 2 overflows, the register is cleared to "0", FF8 is set to "1", and the circuit 6 is operated.
COPYRIGHT: (C)1980,JPO&Japio
JP10390278A 1978-08-28 1978-08-28 Microprogram control device Pending JPS5530786A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10390278A JPS5530786A (en) 1978-08-28 1978-08-28 Microprogram control device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10390278A JPS5530786A (en) 1978-08-28 1978-08-28 Microprogram control device

Publications (1)

Publication Number Publication Date
JPS5530786A true JPS5530786A (en) 1980-03-04

Family

ID=14366347

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10390278A Pending JPS5530786A (en) 1978-08-28 1978-08-28 Microprogram control device

Country Status (1)

Country Link
JP (1) JPS5530786A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58220298A (en) * 1982-06-14 1983-12-21 Mitsubishi Electric Corp Semiconductor integrated circuit incorporating rom

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50114139A (en) * 1974-02-15 1975-09-06

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50114139A (en) * 1974-02-15 1975-09-06

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58220298A (en) * 1982-06-14 1983-12-21 Mitsubishi Electric Corp Semiconductor integrated circuit incorporating rom
JPS6231438B2 (en) * 1982-06-14 1987-07-08 Mitsubishi Electric Corp

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