JPS5659356A - Electronic computer - Google Patents

Electronic computer

Info

Publication number
JPS5659356A
JPS5659356A JP13352279A JP13352279A JPS5659356A JP S5659356 A JPS5659356 A JP S5659356A JP 13352279 A JP13352279 A JP 13352279A JP 13352279 A JP13352279 A JP 13352279A JP S5659356 A JPS5659356 A JP S5659356A
Authority
JP
Japan
Prior art keywords
instruction
bit
trace
generated
execution
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13352279A
Other languages
Japanese (ja)
Inventor
Yutaka Nakajima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP13352279A priority Critical patent/JPS5659356A/en
Publication of JPS5659356A publication Critical patent/JPS5659356A/en
Pending legal-status Critical Current

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  • Debugging And Monitoring (AREA)

Abstract

PURPOSE: To execute a trace of the instruction and attain the debug of software, by providing a trace bit in the program status read register, and generating an interruption at the instant when execution of the instruction has been finished, if said trace bit is set.
CONSTITUTION: A trace bit TR showing execution of a trace is contained inside of the register 1 for maintaining the program status read PSW, at the time of execution of the instruction, the TR bit is set, the AND gate 2 is turned on by a timing signal 00 generated at the starting time of execution of the instruction, and its output 21 sets the FF3. Subsequently, an output 41 for generating an instruction is generated from the AND gate 4 by the timing 02 generated at the ending time of the instruction, the interruption processing is started, at the same time PSW is rewritten, the TR bit is reset, and therefore no interruption is generated by the interruption processing program. PSW is rewritten again by the final instruction of the interruption processing, and the TR bit is set.
COPYRIGHT: (C)1981,JPO&Japio
JP13352279A 1979-10-18 1979-10-18 Electronic computer Pending JPS5659356A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13352279A JPS5659356A (en) 1979-10-18 1979-10-18 Electronic computer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13352279A JPS5659356A (en) 1979-10-18 1979-10-18 Electronic computer

Publications (1)

Publication Number Publication Date
JPS5659356A true JPS5659356A (en) 1981-05-22

Family

ID=15106747

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13352279A Pending JPS5659356A (en) 1979-10-18 1979-10-18 Electronic computer

Country Status (1)

Country Link
JP (1) JPS5659356A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03204737A (en) * 1990-01-08 1991-09-06 Nec Corp Debug circuit of signal processing processor
JPH04104335A (en) * 1990-08-23 1992-04-06 Nec Corp Memory stop trapper

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03204737A (en) * 1990-01-08 1991-09-06 Nec Corp Debug circuit of signal processing processor
JPH04104335A (en) * 1990-08-23 1992-04-06 Nec Corp Memory stop trapper

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