JPS62279438A - Tracking circuit - Google Patents

Abstract

PURPOSE:To make simultaneous tracing of execution information for instruction and for reading or writing to a memory and I/O possible by providing a prefetch counter that indicates the number of instruction prefetches. CONSTITUTION:A status converting circuit 10 supervises status and outputs signals that control a trace memory 8, an address counter 9 and a prefetch counter 11. When execution of instruction fetch is known the circuit outputs a count up signal to the counter 11 and when execution of an instruction is known, outputs a count down signal. Accordingly, the counter 11 indicates number of instructions stored in an instruction queue inside of a microprocessor 1, and the number indicates the number of trace information of instructions existing in a memory 8 and not yet executed. Thus, execution information of instructions according to the order of execution can be traced, and execution information for reading or writing to the memory and I/O can be traced simultaneously.

Description

[Detailed Description of the Invention] 3. Detailed Description of the Invention [Field of Industrial Application] This invention is a debugging tool for microprocessors, etc., in which data contents are stored for all steps of reading the address or writing down instructions executed by a program. [Prior Art] Fig. 3 is a block connection diagram showing a conventional trace circuit disclosed in, for example, Japanese Unexamined Patent Publication No. 58-96356, and in the figure, 1 indicates a microblock. 2 is a memory, 3 is an input/output device (hereinafter referred to as 10), 4 is a microprocessor bus consisting of control signals, address signals, data signals, and status signals output by the microprocessor 1; 5.6.7 is a microprocessor bus A buffer gate for interfacing with the processor path 4, and 14 an address signal output to the microprocessor bus.

A trace memory for storing data signals and status signals; 9, an address counter for counting the address of the trace memory 14; 13, an instruction execution address counter indicating the address of the trace memory 14 at which an instruction has been executed; 12;
monitors the status and trace memory 14. This is a status conversion circuit that outputs a signal to control the address cuff/reference counter 9 and the instruction execution address counter 12.

Next, the operation will be explained. The microprocessor 1 executes the program while repeating the steps shown below.

Step 1S: Read the next instruction to be executed from the memory 2 (hereinafter referred to as instruction fetch).

Step 2S: Memory 2 if necessary depending on the type of instruction.
Or read data from IO3.

Step 3S: Execute the command.

Step 4S: Memory 2 if necessary depending on the type of instruction.
Or write data to IO3.

When the microprocessor 1 has an instruction module for storing instructions internally, step 1S and step 3S can be operated in parallel. FIG. 3 shows a trace circuit intended for such a type of microprocessor 1. First, by initial setting, address power + 7 digits 9. The values of the instruction execution address counter 12 are made to match. When the status conversion circuit 12 learns from the status output from the microprocessor 1 that instruction fetch execution has started, the status conversion circuit 12 outputs a write signal to the trace memory 14, and the microprocessor path 4
The address signal, data signal, and status signal output to the trace memory 14 are stored in the trace memory 14. At the same time, the address counter 9 counts up by typing when the write signal to the trace memory 14 becomes invalid, and specifies the address of the trace memory 14 to be stored. Also,
In parallel with this operation, when the microprocessor 1 learns that the instruction has been executed based on the status output, the status conversion circuit 12 outputs a count amplifier signal to the instruction execution address counter 12, and the instruction execution address counter 13 determines the next execution. The address of the trace memory 14 where the trace information of the instruction to be executed is stored is stored. Furthermore, the instruction execution address? When the instruction to be changed is executed, the status conversion circuit 12 outputs a write signal to the address counter 9 and sets the value of the instruction execution address counter 13 in the address counter 9. Due to this behavior.

The trace information in the next instruction fetch is rewritten on top of the trace information that was not executed, and the trace information of the executed instructions is stored in the trace memory 14 in accordance with the order of execution. In addition, when reading the trace information in the trace memory 14, first read the instruction execution address kakunta 1.
3 is read through the buffer gate 7 to find out how far the trace has progressed, and then the address where the necessary trace information is stored is set in the address counter 9 through the instruction execution address counter 13.

By applying a read signal to the trace memory 14, desired trace information can be read out via the buffer gate 5.

[Problem that the invention seeks to solve]

Since the conventional trace circuit is configured as described above, the execution of instructions can be traced according to the execution order. There was a problem that they could not be performed simultaneously.

This invention was developed to solve the above-mentioned problems, and provides a trace circuit that can simultaneously trace the execution information of program instructions and the execution information of reading or writing to memory or IO. The purpose is to obtain.

〔problem? Means to solve]

The trace circuit according to the present invention stores trace information such as address, data, status, etc. in the trace memory at the time of instruction 7 etching and pass access of read/write to memory or IO, and executes an instruction to change the instruction execution address. When a run occurs, the occurrence information and the instruction prefetch number are stored in the trace memory.

[Effect]

The number of instruction prefetches in this invention indicates the number of next instructions and the number of instruction trace information that were executed even though the instruction was fetched, and is calculated from the time of occurrence and is equal to the number of instruction prefetches.

By ignoring the stored trace information for instruction fetches, it is possible to extract trace information for executed instructions and also obtain trace information for reads/writes to the trace memory and IO at the same time.

[Disaster example]

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, 1 is the Reik α Pro Seven, 2 is the memory, and 3
is an IO, and 4 is a control signal and address signal output by the microprocessor 1.

A microprocessor bus consisting of data signals and status signals, 5 to 7 buffer gates for interfacing with the microprocessor bus 4, 8 designating address signals, data signals, status signals and the number of instruction prefetch outputs to the microprocessor bus; 9 is an address counter that determines the address signal of the trace memory 8; 11 is a prefetch counter that indicates the number of instruction prefetch; and 10 is a status indicator; monitor,
Trace memory8. This is a status conversion circuit that outputs a signal to control the address counter 9 and the instruction prefetch counter 11.

Next, the operation of the present invention will be explained as follows: Does the microprocessor 1 have an internal instruction queue? A case will be described in which the steps 1S and 3S can operate in parallel. When the execution of instruction fetch or reading/writing to memory or IO is known from the status output from the microprocessor 1,
The status conversion circuit 10 outputs a write signal to the trace memory 8, and stores the address signal, data signal, and status signal output to the microprocessor bus 4 in the trace memory 8. At the same time, the address counter 9 registers when the write signal to the trace memory 8 becomes invalid.
Specify the address of the trace memory 8 to be counted up and stored in the primary storage. Also, in parallel with this action,
When the status conversion circuit 10 learns that an instruction fetch has been executed, it outputs a count-up signal to the prefetch counter 11, and when it learns that an instruction has been executed, it outputs a count-up signal to the prefetch counter 11.
Outputs a countdown signal to 1. Therefore, by this operation, the prefetch counter 11 indicates the number of instructions stored in the instruction queue inside the microprocessor 1. This number also indicates the number of trace information of unexecuted instructions existing in the trace memory 8. Furthermore, upon learning of the execution of an instruction that changes the instruction execution address, the status conversion circuit outputs a write signal to the trace memory 8, and stores the generation information and the instruction prefetch number at that time in the trace memory 8. At the same time, the address counter 9 also counts up at the timing when the write signal becomes invalid. 11. When reading trace information from the trace memory 8, first read the values of the address counter 9 and prefetch counter via the buffer gate 7.5.
If you know how far the trace has progressed, set the address where the necessary trace information is stored in the address color/receiver 9, and give a read signal to the trace memory 8.

A desired trace circuit can be read out via the expansion gate 5.

In the trace circuit of the present invention, the trace information of unexecuted instructions is also mixed in the trace memory 8, but as information to remove it, 2 occurrence information and the number of instruction prefetch at that time are stored in the trace. . therefore,
By preparing a simple editing program, it is possible to obtain a trace of instruction execution and reading/writing to memory or IO according to the execution order. Figure @2 shows an editing explanatory diagram when trace information of instructions that are not executed is removed in this way and desired trace information is read out according to the order of execution.

In the above embodiment, the trace information includes address signals, data signals, and status signals, but it goes without saying that information necessary for debugging may be traced. ″
Even if the capacity of the internal instruction queue of the microprocessor 1 changes, it is only necessary to set the prefetch counter to the same capacity, and this can be easily handled depending on the microprocessor.

〔Effect of the invention〕

As described above, according to the present invention, trace information such as address instruction data and status is stored in the trace memory during instruction fetch and read/write bus access to memory and IO, and instructions for changing the instruction execution address are stored in the trace memory. When executed, the generation information and the number of instruction prefetch at that point are stored in the trace memory, so even microprocessors with an internal instruction queue can be configured to follow the execution order. This has the effect that a trace of instruction execution and reading/input to memory and IO can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a block connection diagram of a trace circuit according to an embodiment of the present invention, FIG. 2 is an explanatory diagram for editing trace information stored in a trace memory, and FIG. 3 is a block connection diagram of a conventional trace circuit. In the diagram, 1 is! Microprocessor, 2 is memory, 3
is the IO, 4 is the microprocessor bus, 5 to 7 are the back gate %, 8.14 is the trace memory, 9 is the address counter %, 10.12 is the status conversion circuit, 11 is the prefetch counter, and 13 is the instruction execution address counter. be. Note that in FIG. 1, the same reference numerals indicate the same or complementary parts. Patent applicant: Mitsubishi Electric Corporation, '-co agent: Patent attorney 1) Hiroshi Sawa, 1997
((2 other people) - 1st Figure 4: Microphone 0fu 0 mouth/Tsububasu 3rd Figure 4: My 77O＞mouth/li no＼゛'su Urin Komaba: 2nd Lingyo Dongyo 14 years old Procedural amendment (voluntary)

Claims (3)

[Claims] (1) In a trace circuit for a microprocessor in which instruction execution control and bus access control can operate in parallel,
A trace memory is provided to store the data to be traced,
At the timing when the write signal to this trace memory becomes invalid, an address counter counts up and specifies the address of this trace memory, and a prefetch counter is provided to count the number of instruction prefetches. The status conversion circuit monitors the status related to instruction execution and bus access output by the microprocessor, outputs a write signal to the trace memory, and sends a count up signal and a count down signal to the prefetch counter. A trace circuit characterized in that it is configured to output. (2) The trace circuit according to claim 1, wherein address/data access is stored in a trace memory during bus access. (3) When an instruction that changes the instruction execution address is executed, the occurrence information and the number of instruction prefetch at that time are stored in the trace memory. trace circuit.