JPS60262243A - High-speed arithmetic unit - Google Patents

Abstract

PURPOSE:To reduce the program capacity and to attain a high-speed operation by using the 1st arithmetic circuit having a subtraction function to A and B and the 2nd arithmetic circuit having a subtraction function to B and A respectively. CONSTITUTION:The picture element data Di and D5 are read out of a memory 1 and supplied to the 1st arithmetic circuit 2 having an addition/subtraction function as well as to the 2nd arithmetic circuit 3 having a minimum limit subtraction function. Then Di-D5 and D5-Di are outputted form the circuits 2 and 3 respectively. A multiplexer 4 usually transmits the output of the circuit 2 and then the output of the circuit 3 only in case an absolute value arithmetic instruction is written on a program memory 5 and also a code bit contained in the output of the circuit 2 shows a minus. Thus it is possible to obtain the absolute value of a difference with an instruction of a step.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a digital signal arithmetic device, and more particularly to a device that performs subtraction and absolute value arithmetic at high speed.

Conventional configurations and their problems Many devices that perform digital signal processing have been developed in recent years, but speech recognition, character recognition, graphic processing, etc. are complex processes and require a large amount of data, so they are still not widely used in practical use. It's too late to offer. Particularly in the field of digitally processing video signals, where the amount of data is enormous, the processing device is required to be particularly fast. An example will be explained in which processing is performed by setting a 3×3 pixel window on a screen composed of 512×512 pixels vertically and horizontally. Figure 3 has 612 pixels vertically and 612 pixels horizontally.
It shows a 3×3 pixel window set within a pixel. For convenience of explanation, 1,2 degrees from the upper left pixel...9
It is numbered 0. For example, the calculation for detecting an isolated point due to noise or the like uses the level difference between the central pixel D5 and eight surrounding pixels using the following formula.

This calculation is performed 612x612 times for one screen, that is, 26 times.
The absolute value calculation of the difference IX-Yl is executed 2.36 million times.

FIG. 1 shows a conventional arithmetic unit. A memory 21 that stores pixels; a selection circuit MUX 22 that selectively passes one of the two pieces of data; Arithmetic circuit person LU23 who performs addition/subtraction calculations, etc. Temporary register 24 for storing the output of the arithmetic circuit. Program memory 2 where programs are stored
6. It will be explained below that when the above calculation is executed by the arithmetic device shown in FIG. 1, the execution process requires 7,080,000 steps of processing, which consists of three steps: subtraction, positive/negative determination, and sign inversion. Pixel data Di, D5
are read out from the memory 21 and sent to the arithmetic circuit 23 respectively.
directly and via multiplexer 22. Subtraction is executed in the arithmetic circuit 23 and the value (Di-Ds)
is input to the temporary register 24. Program memory 2
6, the address of the memory 21 and the control signal of the multiplexer 22;

The arithmetic program to be executed in the arithmetic circuit 23 has been written to an appropriate size. The condition JUMP is used as the next step of this subtraction instruction.
An instruction is written to input 0 and (DiDs) through the multiplexer 22 as inputs to the arithmetic circuit 23 if the numerical value input to the temporary register 24 is negative. Furthermore, as the next step, the arithmetic circuit 23 executes subtraction and writes in the program memory 26 a command to add 0 (Di Ds) and store it in the temporary register 24. The conventional calculation device shown in FIG. 1 calculates the first DiDsl in this manner.

The first disadvantage of the arithmetic device shown in FIG. 1 is that it is slow. It takes 3 to 4 program steps.

Because of the high speed, when the program memory 21 is read out with instructions first, at least one step of wasted time occurs due to the condition JUMP. The second drawback is that the processing time is not constant due to the condition JUMP.

For this reason, it is necessary to add a monitoring device that writes new data to the memory 21 while monitoring whether or not a JUMP occurs, or to keep the processing time constant by writing an idle command that does nothing if a JUMP does not occur. is necessary. The third drawback is that the number of steps in the program is long.

OBJECTS OF THE INVENTION It is an object of the present invention to solve the above-mentioned drawbacks and to provide a device that performs high-speed calculations using one-step instructions without using the conditional JUMP instruction in absolute value calculations.

Structure of the Invention The present invention provides a first arithmetic circuit having at least a subtraction function for two input data A and H;
, a second arithmetic circuit having at least a subtraction function for B and A with B replaced, and controlled by an absolute value arithmetic instruction and a sign bit in the output signal of the first arithmetic circuit. The high-speed arithmetic device is characterized in that either the output signal of the first arithmetic circuit or the second arithmetic circuit is outputted via a selection circuit.

DESCRIPTION OF EMBODIMENTS FIG. 2 shows an embodiment of the present invention, and its operation will be explained. FIG. 3 is an explanatory diagram of a method of processing image information. Examples are:
Memory 1 stores data, memory 1 performs numerical operations
．． Second arithmetic circuit 2, 3. Multiplexer 4 that selectively passes only one of the two input signals. and a program memory 6 that stores programs.

Pixel data Di+Ds is read out from memory 1 and
The signal is input to the second arithmetic circuit 2 and also to the second arithmetic circuit 3. The first arithmetic circuit 2 has addition and subtraction functions. On the other hand, it is sufficient that the second arithmetic circuit sFi has at least a subtraction function. In the program memory 6, a subtraction instruction and an absolute value calculation instruction are written in one step. The output of the first arithmetic circuit 2 is (DI Ds), and the output of the second arithmetic circuit 3 is (Ds-Di). These two outputs are input to multiplexer 4. Multiplexer 4td usually the first
However, only when an absolute value calculation instruction is written in the program memory 5 and the sign bit in the output of the first calculation circuit 2 indicates a negative value, the output from the second calculation circuit 2 is passed through. The output of the arithmetic circuit 3 is passed through. As described above, the absolute value of the difference can be obtained with a one-step instruction.

Effects of the Invention According to the present invention, a calculation result can be obtained in a program step that is 10% shorter than the conventional method, so high-speed operation can be performed and the program capacity can be small. Also the condition JUMP
Since there are no statements, it is easy to synchronize the input of data and the output of the arithmetic circuit results.

If the same circuit is used as the second arithmetic circuit and the second arithmetic circuit, the integrated circuit can be designed using a mask without increasing the number of man-hours.

The present invention can provide an arithmetic device suitable for character recognition, image processing, etc.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a conventional arithmetic device, FIG. 2 is a circuit diagram of an embodiment of the arithmetic device of the present invention, and FIG. 3 is a diagram for explaining a method of processing image information. 1...Memory, 2.3... Arithmetic circuit,
4...Multiplexer, 6...Program memory. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
figure

Claims (1)

[Scope of Claims] A first arithmetic circuit having at least an addition/subtraction function for two input cams B, and the two input cams. and a second arithmetic circuit having at least a subtraction function for B and M with B replaced, and a selection circuit controlled by an absolute value arithmetic instruction and a sign bit being output from the first arithmetic circuit. A high-speed arithmetic device, characterized in that only the eleventh arithmetic circuit outputs any of the outputs of the second arithmetic circuit.