JPS5475251A - Logic simulation processor - Google Patents

Logic simulation processor

Info

Publication number
JPS5475251A
JPS5475251A JP14305677A JP14305677A JPS5475251A JP S5475251 A JPS5475251 A JP S5475251A JP 14305677 A JP14305677 A JP 14305677A JP 14305677 A JP14305677 A JP 14305677A JP S5475251 A JPS5475251 A JP S5475251A
Authority
JP
Japan
Prior art keywords
simulation
logic
processor
gate
unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14305677A
Other languages
Japanese (ja)
Inventor
Masayuki Inagaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP14305677A priority Critical patent/JPS5475251A/en
Publication of JPS5475251A publication Critical patent/JPS5475251A/en
Pending legal-status Critical Current

Links

Landscapes

  • Logic Circuits (AREA)
  • Management, Administration, Business Operations System, And Electronic Commerce (AREA)

Abstract

PURPOSE: To shorten the simulation time and thus to increase the simulation velocity by executing the simulation in parallel for more than one unit of the gate.
CONSTITUTION: Main memory 200 which stores the information of more than one unit of the logic chart, the state chart, etc. indicating the logic arithmetic function for the subject gate in the subject circuit which performs a logic simulation plus CPU1 which carries out the pre- and post-processes for the simulation process based on the normal program are connected to logic simulation processor 400 as well as to input/output control part 300 which controls the input/output for the computer system via system interface 500 which carries out the interface for the information. Then an order for simulation process is prepared at the specified area of main memory 200 to give access to processor 400 so that the simulation may be carried out in parallel for more than one unit of the logic gate which can be executed at one time on the invent table via processor 400 and the information prepared at CPU100.
COPYRIGHT: (C)1979,JPO&Japio
JP14305677A 1977-11-28 1977-11-28 Logic simulation processor Pending JPS5475251A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14305677A JPS5475251A (en) 1977-11-28 1977-11-28 Logic simulation processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14305677A JPS5475251A (en) 1977-11-28 1977-11-28 Logic simulation processor

Publications (1)

Publication Number Publication Date
JPS5475251A true JPS5475251A (en) 1979-06-15

Family

ID=15329876

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14305677A Pending JPS5475251A (en) 1977-11-28 1977-11-28 Logic simulation processor

Country Status (1)

Country Link
JP (1) JPS5475251A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4744084A (en) * 1986-02-27 1988-05-10 Mentor Graphics Corporation Hardware modeling system and method for simulating portions of electrical circuits

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4744084A (en) * 1986-02-27 1988-05-10 Mentor Graphics Corporation Hardware modeling system and method for simulating portions of electrical circuits

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