JPS54124947A - Error check system of arithmetic circuit - Google Patents
Error check system of arithmetic circuitInfo
- Publication number
- JPS54124947A JPS54124947A JP3341378A JP3341378A JPS54124947A JP S54124947 A JPS54124947 A JP S54124947A JP 3341378 A JP3341378 A JP 3341378A JP 3341378 A JP3341378 A JP 3341378A JP S54124947 A JPS54124947 A JP S54124947A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- data
- parity information
- arithmetic
- reg
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
PURPOSE: To improve the reliability of a circuit and that of data by comparing parity information at an input side with that added at an output side in a fixed arithmetic mode.
CONSTITUTION: Logic operation circuit ALU fetches data D on input data bus DIN including parity information P to arithmetic register X-REG and performs the logic operation with data of 2nd arithmetic register Y-REG where fixed data have been set previously or input data D inputted onto register Y-REG to output parity information P onto data bus DOUT on the bas is of the arithmetic result. Then, this logic operation circuit ALU is provided with comparator circuit 4 which compares the output of parity information 1 set into register X-REG with parity information P after passing through parity generating circuit 3 on output data bus DOUT. Then, the error of circuit ALU is checked by checking the comparison result of circuit 4 corresponding to arithmetic mode MD of circuit ALU.
COPYRIGHT: (C)1979,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP53033413A JPS6029413B2 (en) | 1978-03-22 | 1978-03-22 | Arithmetic circuit error checking method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP53033413A JPS6029413B2 (en) | 1978-03-22 | 1978-03-22 | Arithmetic circuit error checking method |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS54124947A true JPS54124947A (en) | 1979-09-28 |
JPS6029413B2 JPS6029413B2 (en) | 1985-07-10 |
Family
ID=12385886
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP53033413A Expired JPS6029413B2 (en) | 1978-03-22 | 1978-03-22 | Arithmetic circuit error checking method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6029413B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0319183A2 (en) * | 1987-11-30 | 1989-06-07 | Tandem Computers Incorporated | Parity regeneration self-checking |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01216704A (en) * | 1987-12-31 | 1989-08-30 | Ito Itoko | Quick and correct positioning of processing tool fitting spindle for multi-shaft machine tool and multi-shaft processing equipment |
-
1978
- 1978-03-22 JP JP53033413A patent/JPS6029413B2/en not_active Expired
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0319183A2 (en) * | 1987-11-30 | 1989-06-07 | Tandem Computers Incorporated | Parity regeneration self-checking |
US4872172A (en) * | 1987-11-30 | 1989-10-03 | Tandem Computers Incorporated | Parity regeneration self-checking |
Also Published As
Publication number | Publication date |
---|---|
JPS6029413B2 (en) | 1985-07-10 |
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