JPS5627428A - Error detecting circuit for bilateral bus - Google Patents

Error detecting circuit for bilateral bus

Info

Publication number
JPS5627428A
JPS5627428A JP10330079A JP10330079A JPS5627428A JP S5627428 A JPS5627428 A JP S5627428A JP 10330079 A JP10330079 A JP 10330079A JP 10330079 A JP10330079 A JP 10330079A JP S5627428 A JPS5627428 A JP S5627428A
Authority
JP
Japan
Prior art keywords
bus
bilateral
circuit
data
bilateral bus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10330079A
Other languages
Japanese (ja)
Inventor
Ryuichi Inoue
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP10330079A priority Critical patent/JPS5627428A/en
Publication of JPS5627428A publication Critical patent/JPS5627428A/en
Pending legal-status Critical Current

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  • Hardware Redundancy (AREA)

Abstract

PURPOSE: To realize reduction in hardware by making a comparison between the output of one logical unit connected to a bilateral bus and that of the other logical unit isolated from the bilateral bus via a gate circuit.
CONSTITUTION: Logical unit BALU1 consisting of an arithmetic logical operating circuit and RAM and BALU3 isolated from bilateral bus 101 via gate circuit 2 are provided. When BALUs are read, data in BALU1 are input to comparing circuit 4 by way of bus 101 and data in BALU3, on the other hand, are input to circuit 4 by way of data bus 102. In the constitution like this, circuit 4 compares the contents of bus 101 to those of bus 102 and, when the both disagree, generates a comparison error. Thus, errors of BALUs with the bilateral bus and those of the bilateral bus are detected.
COPYRIGHT: (C)1981,JPO&Japio
JP10330079A 1979-08-14 1979-08-14 Error detecting circuit for bilateral bus Pending JPS5627428A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10330079A JPS5627428A (en) 1979-08-14 1979-08-14 Error detecting circuit for bilateral bus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10330079A JPS5627428A (en) 1979-08-14 1979-08-14 Error detecting circuit for bilateral bus

Publications (1)

Publication Number Publication Date
JPS5627428A true JPS5627428A (en) 1981-03-17

Family

ID=14350391

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10330079A Pending JPS5627428A (en) 1979-08-14 1979-08-14 Error detecting circuit for bilateral bus

Country Status (1)

Country Link
JP (1) JPS5627428A (en)

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