JPS5624645A - Decimal multiplication system - Google Patents
Decimal multiplication systemInfo
- Publication number
- JPS5624645A JPS5624645A JP10027579A JP10027579A JPS5624645A JP S5624645 A JPS5624645 A JP S5624645A JP 10027579 A JP10027579 A JP 10027579A JP 10027579 A JP10027579 A JP 10027579A JP S5624645 A JPS5624645 A JP S5624645A
- Authority
- JP
- Japan
- Prior art keywords
- register
- case
- read
- column
- decimal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
PURPOSE: To reduce the overhead and attain the high speed operation by providing a construction forming a multiplication decimal multiple at the time of requisition.
CONSTITUTION: The content of the multiple corresponding portion of the multiple accommodating register 12 is read by the multiple reading register 2 and then the presence or absence of the multiple is tested. If the multiple is correctly read (in the case of forming the test condition), the content enters the multiplication loop and the contents of the intermediate result accommodating register 1 and the register 2 are added by 6 and the result thereof is obtained by the register 1. Then, the value of the register 1 is shifted by 8 rightward by one column and the one shifted out column is, for example, stored as the calculation result to complete the operation of one column. In the case when the required multiple is not yet calculated, (in the case when the test condition is not established), one multiple of the multiplier is read to the register 2 and after the required multiple is obtained to the register 3 by using the work resist 3 and the decimal adding circuit 6, it enters the multiplication loop and thereafter the calculation is progressed hereinafter similarly.
COPYRIGHT: (C)1981,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10027579A JPS5624645A (en) | 1979-08-08 | 1979-08-08 | Decimal multiplication system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10027579A JPS5624645A (en) | 1979-08-08 | 1979-08-08 | Decimal multiplication system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5624645A true JPS5624645A (en) | 1981-03-09 |
Family
ID=14269642
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10027579A Pending JPS5624645A (en) | 1979-08-08 | 1979-08-08 | Decimal multiplication system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5624645A (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6029865A (en) * | 1983-07-29 | 1985-02-15 | Hitachi Ltd | Logical simulation system by history registration |
JPS60225980A (en) * | 1984-04-25 | 1985-11-11 | Hitachi Ltd | High speed picture processor |
US4745569A (en) * | 1983-12-28 | 1988-05-17 | Hitachi, Ltd. | Decimal multiplier device and method therefor |
JPH02204828A (en) * | 1989-02-03 | 1990-08-14 | Nec Corp | Arithmetic processing unit |
JPH03100826A (en) * | 1989-09-14 | 1991-04-25 | Fujitsu Ltd | Information processor |
-
1979
- 1979-08-08 JP JP10027579A patent/JPS5624645A/en active Pending
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6029865A (en) * | 1983-07-29 | 1985-02-15 | Hitachi Ltd | Logical simulation system by history registration |
JPH0472269B2 (en) * | 1983-07-29 | 1992-11-17 | Hitachi Ltd | |
US4745569A (en) * | 1983-12-28 | 1988-05-17 | Hitachi, Ltd. | Decimal multiplier device and method therefor |
JPS60225980A (en) * | 1984-04-25 | 1985-11-11 | Hitachi Ltd | High speed picture processor |
JPH02204828A (en) * | 1989-02-03 | 1990-08-14 | Nec Corp | Arithmetic processing unit |
JPH03100826A (en) * | 1989-09-14 | 1991-04-25 | Fujitsu Ltd | Information processor |
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