JPH02204828A - Arithmetic processing unit - Google Patents

Abstract

PURPOSE:To execute decimal multiplication at high speed by storing a decimal multiple of a multiplicand operand generated once in a data store means, and skipping the generation of the same decimal multiple of the same multiplicand operand by a flag for showing a fact that the decimal multiple is stored. CONSTITUTION:As for a decimal multiple of a multiplicand operand stored in a data store means 12, '0' hold through 9 holds are stored in accordance with an address '0' through an address 9, respectively. Also, an output of this address register 14 indicates how many folds of decimal multiple is formed to a control storage CS. Moreover, the output of the address register 14 is sent to a register being a flag store means 16 through a decoder 15, and controlled so that the corresponding flag becomes '1', when the decimal multiple is written in the data store means 12. A selector being a branch condition output means 17 selects an output of the flag store means 16 by an output the lower 4 bits of a register 10, and outputs it as a branch condition to the control storage CS. In such a way, decimal multiplication can be executed at high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an arithmetic processing device, and in particular, the present invention relates to an arithmetic processing device, and in particular, the present invention relates to an arithmetic processing device that processes a multiplicand operand and a multiplier operand expressed in binary coded decimal code.
The present invention relates to an arithmetic processing device that performs 0-base multiplication.

[Prior Art] Conventionally, this type of decimal multiplication processing involves multiplying the multiplicand operand by the multiplier operand in decimal digits one by one, and then multiplying the multiplicand operand by the multiplier operand one decimal digit at a time. Add and add. In this arithmetic processing, the value of the decimal multiple of the multiplicand operand required for this arithmetic processing is calculated every time for each digit of the multiplier operand.

[Problems to be Solved by the Invention] In conventional arithmetic processing methods, when the same multiple of the multiplicand operand is used many times, one of the multiplicand operands is
It requires processing time to calculate the 0-base multiple, and as the number of digits in the multiplier operand increases, the processing time increases and the performance deteriorates.

[Means for Solving the Problems] An arithmetic processing device according to the present invention has 10 multiplicand operands.
The decimal multiple is used as part of the read/write address of the decimal digit of the multiplier operand, and corresponds to a data storage means that can be written and read, and an individual storage area for each decimal multiple of the multiplicand operand of the data storage means. Then, 1
a flag storage means for storing a flag indicating whether or not a 0-decimal multiple is stored; a corresponding flag is retrieved from the flag storage means according to the decimal one digit of the multiplier operand;
and branch condition output means for outputting a microinstruction branch condition of a control memory controlling the arithmetic processing unit.

[Example] Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an arithmetic processing device according to an embodiment of the present invention.

The selectors 1 to 5 store the output data of the data storage means 12, the decimal adder 18, and the shifter 19 or the operand data given from the memory (not shown) in the control storage (CS).
) are selected and outputs are given to the data storage means 12 and registers 7 to 10, respectively.

The data storage means 12 is a multi-word storage circuit for storing decimal multiples of multiplicand operands, intermediate results of operations, etc. related to the present invention, and the write/read at and address thereof are given by the selector 13.

This selector 13 selects as its input an address given from the address register 14 or control memory. Here, address register 14 receives as its input the lower 4 bits of register 10, and the lower 4 bits of register 10 are for taking out a single decimal digit of the multiplier operand.

Therefore, in this embodiment, the decimal multiples of the multiplicand operands stored in the data storage means 12 are stored from 0 times to 9 times corresponding to addresses 0 to 9, respectively. The output of this address register 14 also provides the control store with what decimal multiple to generate. Further, the output of the address register 14 is sent through the decoder 15 to a register serving as flag storage means 16.
When a 0-base multiple is written into the data storage means 12, the corresponding flag is controlled to be set to "1". Here, 0 times the multiplicand operand is “0°, which is obtained when the data storage means 12 is reset at the beginning of the instruction, and 1 times is the multiplicand operand itself, so when the multiplicand operand is given from memory, it is Since it is obtained by writing to the address '1'' of the data storage means 12, the value of the flag storage means corresponding to 0 times and 1 times is 1.
It is assumed that m.

A selector serving as a branch condition output means 17 selects the output of the flag storage means 16 based on the output of the lower four bits of the register 10, and outputs it to the control memory as a branch condition.

The decimal adder 18 generates a decimal multiple of the multiplicand operand and adds decimal data involved in the arithmetic processing of decimal multiplication.

The shifter 19 takes out one decimal digit of the multiplier operand and performs the processing of digit alignment of decimal data involved in the arithmetic processing of decimal multiplication.

Further, the selector 6 selects the outputs of the data storage means 12, the decimal adder 18, and the shifter 19 under control of the control storage, and supplies the selected outputs to the register 11.

Here, the register 11 is a register for outputting the calculation result to the memory.

In addition, these registers 7 to 11, data storage means 12,
Setting and resetting of the address register 14 and flag storage means 16 are also controlled by the control memory.

Next, regarding the operation of this embodiment, if the multiplicand operand is “
4375" and the multiplier operand is "233'.

First, at the beginning of the instruction, the data storage means 12, registers 7 to
lO, the bits indicating decimal multiples of 2 to 9 in the flag storage means 16 are reset.

Next, the multiplicand operand is given from the memory and stored at address "1" of the data storage means 12 under the control of the control storage. Then, a multiplier operand is given from the memory, and the address 10 of the register 10 and data storage means 12 is
is stored in

Here, since the lower 4 bits of the register 10 are '31, the branch condition output means 17 outputs 1 of the flag storage means 16.
Outputs the value of the flag corresponding to the decimal multiple of 3, but since it is the first instruction, it naturally outputs '0#', and the control memory generates the decimal multiple before performing arithmetic processing. Branch to microinstruction routine. At this time, register 10
The multiplier operand ``233'' is shifted 4 bits to the right by the shifter 19 and saved as ``23'' at address ``10'' of the data storage means 12, the lower 4 bits ``3'' are stored in the address register 14, and the register 10 is reset. In the microinstruction routine for generating this decimal multiple, first, the multiplicand operand "4375°" is read from the address "1°" from the control memory of the data storage means 12, and stored in the register 7.8. Intermediate results of arithmetic processing of base multipliers (since this is the first processing, there are still “
0") is set to the address "11" of the data storage means 12.
Evacuate to °.

Next, add the values in register 7 and register 8 in decimal, first obtain the decimal multiple of 2 times "8750" and store it in register 7, then add "8750" in register 7 and '4370' in register 8. ’ and the decimal multiple of 3 “131
25", which is stored in register 1 in data storage means 12.
It is stored at the address "3" of the address register 14 with the lower four bits of 0 set, and is also stored in the register 9.

Further, the flag corresponding to the decimal multiple of 3 in the flag storage means 16 is set to "1°," and the
Indicates that a decimal multiple of times is stored.

Next, the decimal multiple of 3 “13” stored in register 9 is
125' performs digit alignment with shifter 19 (in this case,
Since this is arithmetic processing for the first digit, there is no shift by 0 digits. ), are stored in the register 7, and the intermediate result "0" is read from the address "11°" of the data storage means 12 and stored in the register 8.

Next, register 7's '13125' and register 8's '0'
", the result "13125" is stored in the register 8, and the data storage means 12 is added to the address "10
The multiplier operand "23" saved in "23" is read out and stored in the register 10, and the calculation of the first digit of the multiplier operand is completed.

Subsequently, arithmetic processing of the second digit of the multiplier operand is started.

First, since the lower 4 bits of the register 10 are "3 degrees," the branch condition output means 17 outputs the value of the flag corresponding to the decimal multiple of 3 of the flag storage means 16.
A decimal multiple of 3 is generated in the arithmetic processing of the digit, and the value of the flag is '1', so '1'
” is output.

The control memory branches to a microinstruction routine that reads the decimal multiple from the data storage means 12 and performs arithmetic processing. At this time, the multiplier operand m232 of register 10 is shifted to the right by 4 bits by shifter 19 as before.
The lower 4 bits "3" are stored in the address register 14 and the register 10 is reset. In this microinstruction routine, the address where the lower 4 bits of the register 10 are set Using the address "3" of the register 14, a decimal multiple "13125" which is three times the address "3" of the data storage means 12 is read out and stored in the register 9.

Next, the decimal multiple of 3 “13” stored in register 9 is
．． 125”, use shifter 19 to adjust the digits (in this case, 2
Since it is the digit, it is shifted by 1 digit, that is, by 4 bits. ) '131250'' is stored in register 7.

At this time, the difference between the calculation process for the first digit and the first digit is as follows.
Since decimal multiples are not generated, the intermediate results of the arithmetic processing remain in register 8.

Next, “131250” in register 7 and “131250” in register 8
13125° is added and the result “144375” is stored in the register 8. At the same time, the multiplier operand “2” saved at the address “10°” from the control memory is read from the data storage means 12 and is stored in the register 10. Store and complete the calculation up to the second digit of the multiplier operand.

Next, arithmetic processing for the third digit is started, but since the third digit of the multiplier operand is "2" and a decimal multiple has not yet been generated, a decimal multiple similar to the first digit is generated. In this case, since the multiplication operand is the last digit, the result of the decimal multiplication is stored in register 8, not the intermediate result.

Here, the microinstruction processing routine determines that this is the final digit processing, stores it in the register 8 through the selector 6, stores it in the register 11 at the same time, writes it into the memory, and ends the control instruction.

Further, in the above operation example, a decimal multiple of 3 is initially generated, but a decimal multiple of 2 is generated as an intermediate result at this time. Therefore, under the control of the control memory, this decimal multiple of twice is stored in the register 7 and simultaneously stored in the data storage means 12, and the flag storage means 16
By setting the flag corresponding to the decimal multiple of times to 1°,
There is no need to generate a decimal multiple of 2 in the final digit calculation process. In this way, when generating a decimal multiple of a certain multiple, the decimal multiple obtained as an intermediate result is stored in the data storage means, and the flag of the corresponding multiple is set to "1°". In a microinstruction routine that generates multiples, the contents of the multiplier operand
If 0-base multiples are used, it becomes possible to speed up the arithmetic processing.

[Effects of the Invention] As explained above, the present invention stores a decimal multiple of a multiplicand operand once generated in a data storage means, and uses a flag indicating that the same decimal multiple of the same multiplicand operand is stored. By skipping the generation,
This has the effect of speeding up decimal multiplication.

8.9, 10.11...Data register, 12...
Data storage means, 14...address register, 15.
...Decoder, 16...Flag storage means, 17...
Branch condition output means, 18... decimal adder, 19...
・Shifter.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an arithmetic processing device according to an embodiment of the present invention.

Claims (1)

[Scope of Claims] 1. An arithmetic processing unit that performs arithmetic processing based on instructions from microinstructions stored in a control memory, the unit including a decimal multiplicand operand and a multiplier operand expressed in binary coded decimal code. In an arithmetic processing unit that performs multiplication, the decimal multiple of the multiplicand operand is converted into 1 of the multiplier operand.
A data storage means that can read and write a single decimal digit as part of a write address, and a decimal multiple stored in correspondence with each storage area of each decimal multiple of the multiplicand operand of the data storage means. a flag storage means for storing a flag indicating whether or not the multiplier operand is a microinstruction branch; If a decimal multiple of the multiplicand operand, which is used as the value obtained by multiplying the multiplicand operand by a decimal digit of the multiplier operand necessary for the arithmetic processing, is already stored in the data storage means, reading it out; A microinstruction is sent to the flag storage means and the branch condition output means so as to be supplied to the arithmetic processing, and if the decimal multiple thereof is not stored, to newly calculate the decimal multiple and write it to the data storage means and to supply it to the arithmetic processing. An arithmetic processing device characterized by branching.