JP2002182905A - Digital signal processing processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a digital signal processing processor with a simple instruction system and to be easily controlled. SOLUTION: In the digital signal processing processor to execute an operation instruction by a pipeline processing consisting of plural stages, a register 110 exclusive for operation instruction to directly hold an operation result by execution of the operation instruction is provided and the operation instruction is executed by using the held contents of the register 110. In this case, a processing result at a certain stage is directly held and an arithmetic operation is performed by using the held contents at the next stage. No selecting instruction of the register is required since the operation result is directly held in the register exclusive for operation instruction and the instruction system can be simplified. Control becomes easy since the operation results at the previous stages of two operation stages are held as it is and used in the operation results at the following stage.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal processor, and more particularly to a digital signal processor which executes an operation instruction by pipeline processing including a plurality of stages.

[0002]

2. Description of the Related Art The internal structure of a general portable device is shown in FIG. The portable device shown in FIG. 1 has an X memory (X-memo) for storing X data to be calculated.
ry) 101, a Y memory (Y-memory) 102 for storing Y data to be operated on, a P memory (P-memory) 103 for storing a program for the digital signal processor 105, and these memories And a digital signal processor 105 for accessing 101 to 103.

The portable device shown in FIG.
Host CPU (Host CP) that controls the entire device
U) 107, a communication device (Com. Device) 108 that communicates with an external device by wireless or wired,
Keyboard (KB) for inputting and outputting various data,
User interface (User) for interfacing with microphone (MIC) and speaker (SPK)
(I / F) 109, a memory 110 for storing various data, a display 112 for displaying data and the like, and a display controller (Display controller) for controlling the display 112.
(controller) 111 and a memory bridge (Memory br) having a relay function for inputting and outputting various data to and from the digital signal processor 105.
id) 106.

Here, the digital signal processor 1
An example of the configuration 05 will be described with reference to FIG. In FIG. 1, a conventional digital signal processor includes an interface unit 10 for interfacing with a memory and a peripheral circuit (peripheral) not shown, and registers X0 to X0 for storing data from the X memory via an X bus.
Multiplication for performing multiplication with an X register RX composed of X7 and a Y register RY composed of registers Y0 and Y1 for storing data from Y memory via Y bus and storing data from P memory via P bus. (MPY) 1, an arithmetic processing unit 2 that performs shift processing, overflow processing, saturation processing, and the like (shift, ovf, sat) on the multiplication result of the multiplier 1, and an adder (Adde) for performing addition
r) 3 and the addition result of the adder 3 for overflow processing, rounding processing, etc. (zero, ovf, sat,
and an arithmetic unit (ALU) 5 for performing arithmetic and logical operations, comparing and rounding the absolute values of input values, rounding, exchanging, combining, etc. (sat, swap, merge (ab)
s compare) 6, a shifter (shift) 7 for shifting right or left, and an accumulator ACC for holding the results of these arithmetic processing. PAB in the figure is an address bus of P memory, XB
AB is an address bus of the X memory, and YAB is an address bus of the Y memory.

[0005] Registers X0 to X0 constituting the X register RX
X7 has a function of temporarily holding the data of the 32-bit signal line XB and the data held in the accumulator ACC according to the instruction to be executed. Y register R
The registers Y0 and Y1 constituting Y have a function of temporarily holding data of the 32-bit signal line YB according to an instruction to be executed.

The multiplier 1 has a configuration having two arithmetic units for input 8-bit data or a function of performing an operation between 16-bit data. The adder 3 has a function of performing addition of 40 bits or 20 bits. The arithmetic unit 5 has a function of performing an arithmetic operation and a logical operation. This processor is provided with an adder 8 for performing 16-bit addition and absolute value processing, and an arithmetic processing unit 9 for performing rounding processing, overflow processing, and the like (sat, ovf) on the processing result of the adder 8. Sometimes.

[0007] The accumulator ACC is composed of two registers RA and RB which can be accessed from respective arithmetic units arranged in parallel, such as a multiplier 1, an adder 3, and an arithmetic unit 5. Each of the two registers RA and RB has a storage capacity of, for example, 40 bits. To hold the operation result of each operation unit in the accumulator ACC, 2
One of the two registers RA and RB must be specified. It is to be noted that a multiplexer may be provided at a stage preceding each arithmetic unit.

In a digital signal processor having such a configuration, when performing an operation by pipeline processing, the operation results of the arithmetic units arranged in parallel, such as a multiplier 1, an adder 3, and an arithmetic unit 5, are stored in an accumulator. It is held in a designated one of the two registers RA and RB constituting the ACC. The contents held in either of the two registers RA and RB are used for the next arithmetic processing.

[0009]

In the above-described digital signal processor, when the operation result is to be stored in the accumulator, the register must be specified. Therefore, there are drawbacks that not only the instruction length becomes longer and the instruction system becomes complicated, but also the control for selecting a register becomes complicated.

Japanese Patent Application Laid-Open No. H11-112202 describes a configuration in which arithmetic units and general-purpose registers arranged in parallel are connected. Even in the configuration described in this publication, it is necessary to specify a general-purpose register, and there is the same drawback as described above. Also, Japanese Patent Laid-Open No. 2000-
In JP-A-207210, pipeline processing is performed by providing a large-capacity general-purpose register. In this case, in addition to the same drawbacks as described above, since the storage capacity of the general-purpose register is large, the entire processor becomes large. The disadvantage of a large processor is that it is not suitable for application to portable equipment, for example.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned drawbacks of the prior art, and has as its object to provide a digital signal which has a simple instruction system, is easy to control, and can be easily applied to portable equipment. It is to provide a processing processor.

[0012]

SUMMARY OF THE INVENTION A digital signal processor according to the present invention is a digital signal processor for executing an operation instruction by pipeline processing including a plurality of stages. It includes a register dedicated to an operation instruction that is directly held, and executes the operation instruction using the contents held in the register. Since the operation result is directly held in the register dedicated to the operation instruction, a register selection instruction is not required, and the instruction system can be simplified.

Further, the register directly holds a processing result in a certain stage, and performs an operation by using the held content in a next stage. Since the calculation results in the preceding stages of the two calculation stages are held as they are and used for the calculation results in the subsequent stages, the control is simple. Further, the register has a storage capacity for one word which is a processing unit of the own processor. Since it is only necessary to add a register having a storage capacity of one word, the entire processor is not so large as compared with a conventional processor, and for example, a configuration suitable for mounting on portable equipment can be realized.

[0014]

Next, an embodiment of the present invention will be described with reference to the drawings. In the drawings referred to in the following description, the same parts as those in the other drawings are denoted by the same reference numerals. FIG. 1 is a block diagram showing an embodiment of a digital signal processor according to the present invention.
As shown in the figure, the digital signal processor according to the present embodiment has a pipeline processing register 110, unlike the conventional configuration. The pipeline processing register 110 is a dedicated register that can be directly accessed from each processor. Then, when performing the calculation, the result of the calculation is temporarily held using the register 110. For example, when performing a product-sum operation, that is, an operation of first performing multiplication and adding the multiplication results together, the result of the first multiplication is held in the pipeline processing register 110, and the next addition is performed. At times, data is read from the pipeline processing register 110 and used for an operation. In this case, the pipeline processing register 110, which is a dedicated register, is used instead of the general-purpose register.

In the case of a general-purpose register, in order to use the register, it is necessary to specify the register or input data to the register, so that the instruction length becomes long.
On the other hand, in the present system, a dedicated register is provided independently of a general-purpose register. For this reason, a circuit for selecting a register is not required, the control can be simplified, and a register can be specified,
Since there is no need to input data to the register, the instruction length can be reduced.

In other words, in the present system, when performing various operations according to operation instructions, the pipeline processing register 110 is placed in the middle of each operation. As a result, the paths for fetching data are: X register, Y register, X bus, Y bus, pipeline processing, register,
Accumulator and immediate can be freely selected. If, for example, a read cycle and a write cycle are included in one instruction stage, load, execution, and store can be performed simultaneously.

Then, the operation instruction is executed by a plurality of operation units, and the register 110 can be directly accessed from each of the plurality of operation units, and holds the operation result of each operation unit. Furthermore, the plurality of arithmetic units have a register 1
The ten held contents are directly input. By the way, if the pipeline processing register 110 has a storage capacity of, for example, one word, the entire processor is not so large as compared with a conventional processor. Also, since one unit of the arithmetic processing can be held as it is, the control is simple.

The operation of the present system having such a configuration will be described with reference to FIGS. In each of these figures, the instruction inst. 1 to inst. 8 are sequentially executed by pipeline processing. FIG. 2 shows a general execution order of the pipeline processing. As shown in FIG.
t. For N (N = 1 to 8), the prefetch (Pr
Fetch), fetch (Fetch), decode (D
code), access (Access), read (R)
read), execute (Ex1, Ex2), write (Writ)
This is executed by sequentially passing through each stage of e). In this case, the calculation result of the execution Ex1 is
The result is temporarily held in the pipeline processing register 110, and the held operation result is used in the execution Ex2.

That is, since a plurality of operations are executed for one instruction, it is possible to realize a processor which executes more operations with one instruction. Further, since a plurality of operations are performed for one instruction, the operating frequency of the processor can be reduced. Since the operating frequency can be reduced, operation can be performed with a lower power supply voltage, and power consumption can be reduced.

FIG. 3 shows a product-sum operation, that is, a case where addition is performed after multiplication. In FIG.
The execution Ex1 in the middle is multiplication (MPY), and the execution Ex2 is addition (ADD). That is, in the figure, one instruction inst. N (N = 1 to 8) represents prefetch (PrFetch), fetch (Fetch), decode (Decode), access (Access), read (Read), multiplication (MPY), addition (ADD), and write (Write). It is performed by passing through each stage in turn. Also in this case, the operation result of the multiplication MPY is temporarily stored in the pipeline processing register 110.
, And the held operation result is used in the addition ADD.

FIG. 4 shows a case in which four data are added and then divided by a numerical value "4". This operation is used in motion compensation in the well-known MPEG operation. In the drawing, two cases are shown: a case where both execution Ex1 and execution Ex2 in FIG. 2 are addition (ADD), and a case where execution Ex1 is addition (ADD) and execution Ex2 is arithmetic right shift (ASR). Shows three different instruction executions. That is, in FIG. N
(N = 1, 2, 4, 5, 7, 8) is the prefetch (P
rFetch), fetch (Fetch), decode (Decode), access (Access), read (Read), addition (ADD), addition (ADD), and write (Write). Then, the next instruction inst. N (N =
3, 6) are prefetch (PrFetch), fetch (Fetch), decode (Decode), access (Access), read (Read), and addition (AD).
D), right 2 bit shift (ASR), write (Writ)
This is executed by sequentially passing through each stage of e). In this case, as shown in FIG.
By performing a right two-bit shift process on the result obtained by adding the data B, the data C, and the data D, a process of adding the four data A, B, C, and D and then dividing by the numerical value “4” is realized. . Also in this case, the addition A
The operation result by the DD is temporarily stored in the pipeline processing register 110, and the addition A is performed by using the held operation result.
Perform DD. Further, the operation result of the addition ADD is temporarily stored in the pipeline processing register 110, and the stored addition result is subjected to a process of shifting right by 2 bits.

As described above, in the present system, the multiplier 1,
For each of the arithmetic units arranged in parallel, such as the adder 3 and the arithmetic unit 5, any of the arithmetic units is a pipeline processing register 110.
And accumulator ACC.
Further, the number of pipeline stages of the operation is set to a plurality of stages (2
Column). Since the combination of the arithmetic units in the multi-stage pipeline can be freely selected, it can be executed in any of the cases of FIGS.

There is no need to prepare an instruction for selecting the register, the instruction length is shortened, and the instruction system is simplified. Therefore, the overall control is simplified. Further, since a circuit configuration for selecting the register is not required, the configuration of the entire system is simplified. As described above, the present processor uses registers that can be directly and exclusively accessed from each arithmetic unit, so that the instruction length can be shortened by not including the instruction to select a register, and the instruction system does not increase. It is.

Regarding the description of the claims, the present invention can further adopt the following aspects. (1) The operation instruction is executed by a plurality of operation units,
The digital signal processor according to claim 1, wherein the register is directly accessible from each of the plurality of arithmetic units, and holds a calculation result of each of the arithmetic units. (2) The digital signal processor according to (1), wherein the contents held in the register are directly input to the plurality of arithmetic units.

[0025]

As described above, the present invention uses registers which can be directly and exclusively accessed from each arithmetic unit, so that there is no need to prepare an instruction for selecting the register, and the instruction length is reduced. Shorter and easier instruction system. Therefore, there is an effect that the whole control is simplified. Further, since a circuit configuration for selecting the register is not required, there is an effect that the configuration of the entire system is simplified.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a digital signal processor according to the present invention.

FIG. 2 is a diagram showing a general execution order operation example of pipeline processing in the digital signal processor of FIG. 1;

FIG. 3 is a diagram illustrating an operation example of the digital signal processor of FIG. 1;

FIG. 4 is a diagram showing another operation example of the digital signal processor of FIG. 1;

FIG. 5 is a diagram showing an operation used in motion compensation in a well-known MPEG operation.

FIG. 6 is a block diagram illustrating an internal configuration of a general portable device.

FIG. 7 is a block diagram showing a configuration of a conventional digital signal processor.

[Explanation of symbols]

 Reference Signs List 1 multiplier 2 arithmetic processing unit 3 adder 4 arithmetic processing unit 5 arithmetic unit 6 comparator 7 shifter 110 pipeline processing register ACC accumulator RX X register RY Y register

Claims (3)

[Claims] 1. A digital signal processor for executing an operation instruction by pipeline processing including a plurality of stages, comprising: a register dedicated to an operation instruction for directly holding an operation result by execution of the operation instruction; A digital signal processor which executes the operation instruction by using held contents. 2. The digital signal processor according to claim 1, wherein the register directly holds a processing result in a certain stage, and performs an operation by using the held content in a next stage. 3. The digital signal processor according to claim 1, wherein the register has a storage capacity of one word which is a processing unit of the own processor.