JPH02181821A - Arithmetic device - Google Patents

Abstract

PURPOSE:To execute a complicated operation by means of a basically same algorithm and to improve a high speed and the reliability of an operation procedure by previously storing an operation result in a storage device. CONSTITUTION:An arithmetic device for special operation 10 consists of a storage device 11, an address input terminal 12 and an output terminal 13. The storage device 11 previously stores the target special operation result in an area designated by an address and executes the operation by calling a storage content with an operation instruction. Namely, the basic operation result such as addition, subtraction, multiplication and division is previously stored in the storage device 11 of the private arithmetic device 10. By inputting the operand to the address input terminal 12 of the arithmetic unit 10 as it is, the storage content is called and is obtained from the output terminal 13. Thus, the arithmetic unit with the high operation speed and with easy constitution can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to an arithmetic device with high arithmetic speed and simple configuration.

(Prior Art) Numerical operations such as addition, subtraction, multiplication, and division using electronic computers have conventionally been performed using various methods. A simple calculator such as a microcomputer performs various operations by repeating the basic operation of inputting two operands stored in a register into an adder to obtain an addition result using a machine language software program. ing.

A typical calculation method used in large computers is called a microprogram control method.

FIG. 5 shows a block diagram simply illustrating this method. Here, 1 is a decoder that encodes an operation instruction (instruction), 2 is a microprogram storage device (hereinafter simply referred to as storage device), 3 is an adder, and 4 is a register for data (operands) to be operated.

In this system, a series of procedures necessary for calculations are stored in the microprogram storage device 2. Normally, this storage device 2 is a read-only memory (ROM).
) etc. are used. When an arithmetic instruction enters this arithmetic unit, it is encoded by a decoder 1 and input to a storage device 2. Each memory cell of the memory device 2 specifies a memory cell in which an instruction to the adder 3, an instruction to the register 4, and the next operation procedure necessary for the operation are stored.
Your address etc. are written there. Operations such as addition, subtraction, multiplication, and division are executed by passing the operands in the register 4 through the adder 3 several times according to the stored contents.

According to this method, there is no need to write a software program in machine language for the details of the calculation procedure, and the firmware program stored in the ROM automatically executes the program. Therefore, software programming has become simpler and more efficient. Furthermore, since there is no need to send the calculation procedure as a program, the calculation can be executed at high speed.

The two representative methods described above are both based on the same principle of performing calculations by repeatedly using the adder 3. Therefore, for both methods, from the time the instructions are input to the computer until the calculation results are output,
■Delay time Td in decoder 1, ■Delay time (access time) Tm in storage device 2, ■Delay time Ta in adder 3, ■Time T to store the output of adder 3 in register 4
r, is required, and ■■■ is repeatedly executed until the calculation procedure is completed. If the number of repetitions is n, the total time Tt required to complete one operation can be written as Tt=Td+n.(Tm+Ta+Tr). In the microprogram method,
The speed of the program is only increased by converting it to hardware.

[Problem to be solved by the invention]

As described above, an arithmetic device using this type of method requires a different and complex program for each operation, the number of repetitions n varies depending on the operation, and the operation time varies.
Moreover, there were problems such as the need for a long time. For example, since the addition operation ends when n=1, there is no major problem. However, the multiplication operation requires repeated operations n times that are proportional to the bit length of the operand. In subtraction and division, the number of repetitions n becomes even greater.

Furthermore, for high-speed computers, dedicated high-speed multiplier LSIs have been developed, and the 0 multiplier, in which multiplication is performed in the multiplier without passing through adder 3, is relatively simple. This is because it can be converted into hardware based on logic. However, algorithms for subtraction, division, and other functional operations are difficult, and in the current situation where specialized LSIs have not been developed, examples such as multipliers are rather an exception.

As described above, the arithmetic device as a whole does not have a high-speed device configuration and a uniform system.

An object of the present invention is to provide an arithmetic device that is high-speed as a whole and has a unified system.

(Means for Solving the Problems) An arithmetic device according to the present invention includes an address input terminal for inputting operand data to be subjected to an operation as address data, and a memory that stores the operation results in advance in an area specified by the address. It is equipped with an area and an output terminal that outputs an operation result according to operand data.

Furthermore, the present invention is provided with a selection terminal for selecting and non-selecting devices.

Further, according to the present invention, by including at least two or more of this type of arithmetic units and providing selection circuits for these arithmetic units, a general-purpose arithmetic unit capable of performing various operations can be constructed.

Furthermore, by combining the present invention with a conventional microprogram-controlled arithmetic device, a general-purpose arithmetic device having the characteristics of each device can be constructed.

[Effect]

In this invention, when data to be operated on is directly input to the address input terminal, the operation result is immediately output from the storage device, and this is displayed on the output terminal. Furthermore, devices can be selected or unselected using the selection terminal.

If there are multiple storage devices, the selection circuit selects the target storage device.

Furthermore, for calculations that can be processed more quickly using a microprogram control system, the present invention can be combined with a microprogram control device to perform calculations that have the characteristics of each.

〔Example〕

FIG. 1 is a block diagram showing a first embodiment of the present invention.

In this figure, reference numeral 10 denotes a specific calculation arithmetic unit according to the present invention, and a storage device 11. It consists of an address input terminal 12 and an output terminal 13. The storage device 11 stores a specific operation result of interest in an area specified by an address in advance, and performs an operation by calling the stored contents together with an operation instruction.

This invention stores basic operation results such as addition, subtraction, multiplication, and division in advance in the storage device 11 of each dedicated arithmetic unit 10, and inputs the operands as they are to the address input terminal 12 of this arithmetic unit 10. , the stored contents are recalled and the solution is obtained from the output terminal 13.

FIG. 2 is a block diagram showing a second embodiment of the invention. This is an example of an arithmetic unit 10 configured for the purpose of 2-bit multiplication. 14 is a selection terminal of this arithmetic device 10;
15 is a 16-bit memory element. In this embodiment, the 16-bit memory elements 15 are composed of four sets, and together constitute the memory device 11 of the arithmetic unit 10. Each memory element 15 has four input terminals (A
o, A+, A2, As) and one output terminal is output. As shown in FIG. 2, the input terminals are grouped into bits and constitute address input terminals 12 (Ao, A+, A2, As) of the arithmetic unit 10. Further, all the output terminals 13 are taken out independently, and the output terminals 13 (OO, Ol, 0
2.03). It is a 64-bit storage device with a so-called 4 bits x 16 bits bit configuration.

Note that the selection terminal 14 is required when selecting one of the plurality of storage devices 11 of the present invention in the arithmetic unit 10, so its function will be explained in FIG. This will be explained in examples.

In Fig. 2, as a specific example of multiplication, operand A “1
The input and output signals when multiplying by 0'' and B''11' are shown together. The operand signals A and B are input to the address input terminal 6 as they are. For example, (Ao, AIl
A2. Input as follows: AIl)=(1011). The calculation result A) kB is output from the output terminal 13 consisting of four (Oo
, 0+ , 02 , Os )=(0110). The calculation results are written in advance in the storage device 11 so that they can be output in this form.

It is clear that if such an arithmetic unit 1Q is used, not only addition, subtraction, multiplication, and division, but basically any logic/operations and special function operations are possible.

In particular, the required number of digits can be guaranteed in advance for division and special functions, and the calculation results are clear, making it possible to estimate errors extremely accurately.

FIG. 3 is a third embodiment of the present invention, and is a block diagram simply illustrating a general-purpose arithmetic unit 1o incorporating a plurality of storage devices 11 shown in the first embodiment. Here, 1 is a decoder that encodes an operation instruction into a microcode (a selection signal for the storage device 11 and an operand data selection signal), 4 is a register for the data (operand) to be operated, and 11 is shown in FIG. , is a storage device similar to that shown in the embodiment of FIG. 2, and is dedicated for multiplication or division. These storage devices 11 enter the operating state (selected) by receiving the microcode (selection signal) output from the decoder 1 at the selection terminal 14.
It turns out.

The third embodiment of the present invention has the above-mentioned configuration, so that when an instruction is input to the decoder 1, it is translated into a selection signal and sent to the target storage device 11 and register 4. Select data. The storage device 11 that has received the selection signal receives the data sent from the register 4 at the address input terminal 12, returns the calculation result to the register 4, and ends the calculation.

In this way, in this third embodiment, the storage device 1
The calculation progresses extremely easily in one cycle time of 1. Considering that a ROM is used as the storage device 11, it is possible to use a ROM whose one cycle time is approximately the same as that of a ROM used in the microprogram system. In comparison, with conventional microprogram-based arithmetic devices, it takes one cycle to call the microprogram from ROM to perform a single operation.
The operation then requires one cycle. In a normal operation, the result is obtained by repeating this process many times. Therefore, this third embodiment can perform faster and more reliable calculations than conventional calculation devices.

FIG. 4 is a fourth embodiment of the present invention, and is a block diagram schematically showing an arithmetic device 10 in which the storage device 11 shown in the first embodiment is incorporated into a microprogram type arithmetic device. . Here, 1 is a decoder that encodes an operation instruction (instruction), 2 is a microprogram storage device 53 is an adder, 4 is a register for data (operand) to be operated, and 11 to 14 are the same as in FIG. 3. .

This fourth embodiment has the above configuration, so when an instruction is input to the decoder 1,
Here, it is translated into a selection signal to select data in the storage device 11, microprogram storage device 2, or register 4. The storage device 11 that has received the selection signal receives the data sent from the register 4 at the address input terminal 12, returns the calculation result to the register 4, and ends the calculation.

In this fourth embodiment, addition operations that can be processed faster by using the microprogram method are calculated using this method. By using this, the aim is to achieve overall high speed.

(Effects of the Invention) As explained above, since the arithmetic device of the present invention stores the arithmetic results in the storage device in advance, no matter how complex the arithmetic operations, such as special functions or matrices, The algorithm has the feature that it can be executed in the same amount of time. Furthermore, since there is no need to refer to the storage device in which the microprogram is stored, this time is omitted, and the device as a whole is characterized in that it can achieve high speed and improve the reliability of the calculation procedure.

Furthermore, the required number of digits can be guaranteed in advance for division and special functions, and the calculation results are clear, making it possible to estimate errors extremely accurately. reliability can be improved.

If the device has a selection terminal, the device can be selected or unselected.

Further, since the present invention includes two or more storage devices and allows the user to select and use these devices, it is possible to provide versatility.

Furthermore, in this invention, it is possible to select and perform arithmetic operations using a microprogram, so if the arithmetic processing is faster than from a storage device, the microprogram control method can be used, which has the advantage of speeding up the overall processing. be.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a first embodiment of the invention, FIG. 2 is a block diagram showing a second embodiment, and FIG. 3 is a block diagram showing a third embodiment of the invention. Block diagram of an arithmetic device incorporating a plurality of arithmetic devices shown in the embodiment, No. 4
The figure shows a fourth embodiment of the present invention, and is a block diagram of a microprogram type arithmetic unit incorporating the arithmetic unit shown in the first embodiment, and Fig. 5 is a block diagram of a conventional microprogram type arithmetic unit. It is a block diagram. In the figure, 1 is a decoder that encodes arithmetic instructions, 2 is a microprogram storage device, 3 is an adder, 4 is a register for data (operands) to be added, 10 is an arithmetic device, 11 is a storage device, 12 is an address input terminal, 13 is an output terminal, 14 is a selection terminal, 15 is 16
It is a bit storage element.

Claims (4)

[Claims] (1) An address input terminal that inputs the operand data to be operated on as address data, a storage area that stores the operation results in advance in the area specified by the address, and an output that outputs the operation results according to the operand data. 1. An arithmetic device comprising a storage device comprising a terminal. (2) An address input terminal that inputs the operand data to be operated on as address data, a storage area that stores the operation results in advance in the area specified by the address, and an output that outputs the operation results according to the operand data. 1. An arithmetic device comprising a storage device having a terminal and a selection terminal for selecting or non-selecting a device. (3) A selection device including at least two arithmetic devices according to claim (2), a selection device for these arithmetic devices, a selection device for a storage device in which operand data is stored, and a register for storing calculation results. An arithmetic device characterized by comprising a selection of. (4) An arithmetic device comprising at least one arithmetic device according to claim (2), which arithmetic device is selected and performs an arithmetic operation under microprogram control.