JPS5921068B2 - Program step calculation method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a program step calculation method for detecting remaining program capacity in a program computer with a small storage capacity by calculating remaining steps.

In general, small electronic calculators, especially electronic desktop calculators (hereinafter referred to as calculators), usually perform a series of arithmetic operations using three fixed programs installed in advance. In order to easily process this, so-called programmable calculators, which can be programmed with predetermined programs for each flight, are being put into practical use. However, since such calculators with programs are small, their storage capacity cannot be increased very much, and the program storage area is generally small. Therefore, when writing multiple programs, it is difficult to increase the storage capacity. It is necessary to judge whether all the programs to be written can be written. However, with conventional programmable calculators, it is difficult to know in advance whether all the programs to be written can be written. There is nothing that can be done, but simply an "error" when the program is written beyond its storage capacity.
There is something to display! It wasn't too much.

If the program storage capacity is exceeded while the program is being written, the written program cannot be used, resulting in wasted time. In addition, the fact that it is only known during the writing process whether or not the program can be written as described above always causes anxiety when operating the program, and furthermore, it is not possible to use the program storage area effectively. There were various drawbacks such as: The present invention has been made in view of the above-mentioned current situation, and is aimed at detecting the unstored capacity in which no programs are stored yet by calculating the remaining program steps in a small electronic calculator with a program that can store a plurality of programs. The purpose of this invention is to provide a program step calculation method that can perform the following steps. An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a circuit block diagram for explaining the outline of the gist of the invention prior to a detailed explanation of the invention.

That is, the program stored in advance in the program register 1 is sequentially addressed by the address register 2 and read out. Further, the output of the address register 2 is the output from the key input device 3 including the program key to the control circuit 4.
is controlled by supplying the address register 2 via the address register 2. Further, the maximum number of program steps corresponding to the maximum storage capacity inherent to the program register 1 is determined by the code generation circuit 5, which is set by the output from the control circuit 4 at the time the address register 2 is cleared. The output for setting the maximum step is stored in the display register 6. Then, the contents of the program read from the program register 1 are input to the instruction register 7 and temporarily stored, and the output is further sent to the judgment circuit 8 which judges the presence or absence of stored information. . The judgment output is input to the control circuit 4. Thus, in response to the output of the judgment circuit 8, the control circuit 4 increments the address of the address register 2 by one step when the judgment result indicating that there is stored information is input from the judgment circuit 8. Display V
Control is performed to subtract one step from the maximum number of steps input to the register 6. Thereafter, the address register 2 is incremented one step at a time, and the display register 6 is subtracted one step at a time, and the contents of the program register 1 addressed by the address register 2 are read out by the instruction register 71/C. The above operations are repeated until the judgment circuit 8 detects that there is no stored information. Therefore, if there is an unstored area in the program register 1, the display register 6 will display the number of steps. In the above operation, the operator can determine the number of steps in the unstored area by simply operating the program designation key, and can determine whether a new program can be stored in the program register 1.

An embodiment based on the specific configuration of the present application briefly described above will be described with reference to FIGS.

The reference numerals in FIG. 2 do not correspond to those in FIG. 1, and will be described as a new independent embodiment. The block configuration diagram in FIG. 2 shows an example of the overall configuration of a small electronic calculator with a program, and the key input unit 1 includes a numeric key 1, a function key 1, Pr, ENT, ANS:
The output signal from the key manual section 1 is R which specifies the address of ROM 3 which will be described later.
Input to OM address section 2. This ROM address section 2 is a ROM address section 2 in which various microprograms are installed.
M3, and this ROM3 has an output line 4 that outputs a register designation signal, an output line 5 that outputs various instruction commands such as transfer commands, arithmetic commands, and digit shift commands, and corresponds to the above-mentioned key operations. An address designation command following an arbitrary address of the ROM 3 is sent to the output line 6 for outputting the data and other data codes, the output line 7 for outputting a predetermined timing signal, and the ROM address section 2. An output line 8 is provided for outputting. Note that each of the output lines 4 to 8 is a bus line. The register designation signal outputted from the output line 4 is sent to the register output and input designation decoders 9 and 10, and the instruction command outputted from the output line 5 is sent to the instruction decoder 11. .

Further, the data output from the output line 6 is sent to the code generation circuit 1 along with the sequential pulse from the timing counter 14.
The timing signal output from the output line 7 is sent to the timing circuit 13 together with the pulse from the timing counter 14. Furthermore, the output from the output line 8 is input to the ROM address section 2, and the output from the ROM
Specify the next address after 3. By the way, the instruction decoder 11 decodes the instruction command output from the ROM 3, and according to the decoding result, sends instructions to the output and input specifying encoders 9, 10, gate circuits 15, 16, and adder circuit 17. Each of them supplies an opening/closing control signal and an operation command output such as an addition/subtraction command.

Further, the code generation circuit 12 converts, for example, the 4-bit parallel zeta input from the ROM 3 via the output line 6 as described above into a serial code synchronized with the sequential pulse from the timing counter 14 and outputs the serial code. The output from the code generation circuit 12 is sent to the add path 17 via the gate circuit 18. The timing circuit 13 outputs a 4-bit parallel timing signal from the ROM 3 in synchronization with the sequential pulse from the timing counter 14, and also outputs the memory column designation address from the gate circuit 15 to a predetermined value, as will be described later. It is output at timing, and the output is sent to the register designation decoders 9 and 10. The output from this register output designation decoder 9 performs gate opening/closing control for the gate circuit 18, and the register input designation decoder 10 outputs the output from X, Y, Z.
calculation registers 19, 20, 21, flag register 22 for address storage, instruction register 23 for temporarily storing the contents of the addressed program, data memory 24 for storing data, and program storage. It controls the opening and closing of gates of gate circuits 26 to 32 provided on the input side of the program memory 25, and also controls the opening and closing of a gate circuit 33 provided on the input side of an address register 34, which will be described later. Further, the respective outputs of the registers 19 to 23 and the memories 24 and 25 are connected to the gate circuit 18.
8 selects these inputs under the control of the register output designation decoder 9 as described above, and sends the output to the adder circuit 17.
send to

The adder circuit 17 includes the instruction decoder 1
1 to execute various calculations, and send the outputs to the respective registers 19 to 23 via the respective gate circuits 26 to 32.
and are inputted to each memory 24, 25, and inputted to an address register 34, which will be described later, via a gate circuit 33,
Further, the signal is input to a determination circuit 37, which will be described later, via the gate circuit 16. Therefore, all data transfers between registers, memories, etc. are performed via this adder circuit 17. The address register 34 is composed of, for example, 1 byte (8 bits).
The output from the gate circuit 18 is returned to the input side of the gate circuit 18, and the output terminals of the upper four bits are a 4-bit upper register 35 for temporarily storing the upper address, and the output terminals of the lower four bits are A 4-bit lower register 36 for temporarily storing a lower address is connected.

Then, the output of the upper register 35 is output from the gate circuit 3.
1 and 32, and is also sent to the gate circuit 18, specifying a row in the data memory 2{ and program memory 25. Further, the output of the lower register 36 is sent to the timing circuit 13 via a gate circuit 15 whose opening and closing are controlled by the output of the instruction decoder 11. Further, the output of the adder circuit 17 is transmitted to the instruction decoder 11 and the timing circuit 13.
The signal is sent to a judgment circuit 37 which detects and judges the presence or absence of data or carry through the gate circuit 16 which is gate-controlled in accordance with a command from the judgment circuit 37. is sent to the ROM address section 2. On the other hand, the X register 19 also functions as a display register, and its output is sent to the display device 40 via a serial/parallel conversion circuit 38 and a decoder 39.
will be sent and displayed. Furthermore, due to the circuit configuration described above, the program register 25 has, for example, 32 rows x 16 columns and a storage capacity of 256 steps, and has a memory capacity of 256 steps.
The contents of one step of the program are stored in a byte (2 digits). Next, the operation of calculating the program steps of the above-mentioned small electronic calculator with a program will be explained using the following program example.

Program example Prl: (Program number is 1.

) ENTl:2: (The variable human power is memory address 1 and 2.

)3=1×2: (The result of address 3 1fC1 address X2 is entered.

) ANS3: (The answer is number 3.)

) END (The end.

) First, when the program instruction key of the key input section 1 is operated in order to write the program, the FBO (bottom) of the address register 34 and the flag register 22 for address storage is activated, as shown in operation step S1 of the flowchart of FIG. 2 digits) Clear the contents of the area.

That is, when the program instruction key (PrZ) is operated to set a predetermined address in the ROM address section 2, the ROM 3 outputs each control signal to write "0" into the FBO area of the address register 34 and the flag register 22. The instruction decoder 11 generates a register write signal.
Further, the timing output from the timing circuit 13 is obtained, and outputs are generated from the register output designation decoder 9 and the input designation decoder 10, respectively. Also, at this time, the code generation circuit 12 outputs the ``0y'' code. This "0y" code is then written into the FBO areas of the address register 34 and the flag register 22 via the gate circuit 18 and adder circuit 17, and these registers 19 and 34 are cleared as a result. Next, the maximum number of program steps (256 in this embodiment) output from the code generation circuit 12 is input to the Xu area of the X register 19 via the gate circuit 18, adder circuit 17, and gate circuit 26. In operation step S, the contents of the "0,0" address specified by the upper and lower registers 35 and 36, in which the output of the address register 34 is temporarily stored, are read from the program register 25 and output from the ROM 3. The gate circuit 18 operates to transfer the contents of the "0,0" address of the program register 25 to the instruction register 23 according to various instructions, and the adder circuit 1T (this adder circuit, as mentioned above, does not simply transfer data). (also used when executing) and is transferred to the instruction register 23 via the gate circuit 30. However, since nothing is currently written to the program register 25, the instruction register 23 is written with "0". Then, in operation step S3, the contents of the instruction register 23 are outputted from the ROM 3 to the judgment circuit 3T via the gate circuit 18, adder circuit IT, and gate circuit 16 that operate according to control signals for judgment. The decision circuit 37 makes a decision based on the transmitted and stored data, and the result is [NO]. Therefore, judgment circuit 3?
Karapa displays the contents of the X register 19 and sends a signal to specify the address to enter the program input state.
Output to M address section 2. The ROM 3 addressed by the ROM address section 2 performs control to display the contents of the X register 19, and displays the contents of the X register 19 on the display device 40 via the parallel-to-parallel conversion circuit 38 and the decoder 39. is displayed. As mentioned above, the control of the program input state is output from the ROM 3, so that the code corresponding to the program instruction key (Pr key) is specified in the upper and lower registers 35 and 36 (0, 0) of the program register. 25 is stored on the lower side of the address "0,0" as shown in FIG. 3, and is also input to the lowest digit of the The number 2 256 and "P" indicating that the program instruction key (Pr key) has been operated are displayed. By displaying this number of remaining steps, 256, the operator knows that it is possible to write a program with 256 more steps, and the program to be inputted, for example, the above program example, is partially stored in the program memory. It is possible to recognize that it is possible to write data without exceeding the memory capacity of 25.

Next, the display state when each key of the key input unit 1 is actually operated according to a program example will be explained.

Now, set the program number to 1, so key input section 1
When the number key "1" is operated, the display register 19 carries up the already input "P" and inputs "1".

The display state at this time is shown in FIG. 5b. Next, operate the ":" (colon) key to separate the contents of the program, and as shown in FIG. 3, the upper and lower registers 35.
``1, Pr'' is stored in the ``0,0'' address of the program memory 25 specified by 36, and the program content is written to ``0,0'' add. Since the steps have been used, the number of steps used is displayed in the Xu area of the display device 40.
Therefore, when the keys of the key input section 1 are operated in the order shown in the above program example, the display will correspond to the operated key in the lower area where the number of steps used is smaller in the Xu area as shown in cmf in Figure 5. If the code to be used is 1 and 1, it will be displayed between 1 and 1. This corresponding code is shown in the table below. Then, when all the above program examples have been assembled (when the END key is pressed)
The display ends when the number of steps used becomes 16, as shown in FIG. At this time, the program memory 25 stores it in a state as shown in FIG. Unfortunately, when writing a program, "M" is added to the lower side if the program content specifies the at Vs of the data register, and "F" is added to the lower side if it represents a function. Also, although it can only be expressed on the lower side, the upper side is [0]. The operation when program 1 is written into program memory 25 and then program 2 is written will now be described.

Now, to write program 2, program instructions (Pr
) key, the address V register 34 and the FB of the flag register 22 are activated in step S1 in the same manner as described above.
The O area is cleared and the maximum number of steps (256) is stored in the Xu area of the Xv register 19.

Then, the contents [1,Pr'' of the address [0,0] of the program memory 25, which is addressed by the upper and lower registers 35 and 36 that temporarily store the contents of the address register 34, are read out in operation step S2. and is transferred to the instruction register 23 in the same manner as above.
The contents of the instruction register 23 are sent to the determination circuit 37 in operation step S3, and it is determined whether or not there is stored information. Now that “1, Pγ] is read out, the judgment result in the judgment circuit 37 is “YES”.
Then, the process advances to operation step S4. Operation step S4 advances the address by one step, and includes an operation of adding 2 to the FBO area of the flag register 22 and
An operation is performed to transfer the contents of the O area to the address register 34. That is, a signal specifying the flag V register 22 is sent from the ROM 3 via the output line 4, an addition instruction signal and a register input instruction signal via the output line 5, and a code signal and output corresponding to the numerical value 2 via the output line 6. Byte O (that is, FBO area designation) is outputted via line 7, and these control signals cause the contents of the FBO area of flag V register 22 to be transferred to one input terminal of adder circuit 17 via gate circuit 18. The numerical value "2" outputted from the code generation circuit 12 is inputted to the other input terminal of the adder circuit 17 via the gate circuit 18, and an addition instruction is outputted from the instruction decoder 11. As a result, the operation “0,0+0,2” is executed and the result is “0,
2” is again sent to the flag register 2 via the gate circuit 29.
It can be placed in the FBO area of 2. However, this “0,2
” are gate circuit 18, adder circuit 17 and gate circuit 3
3 to the address register 34. Then, in operation step S5, the contents of the Xu area storing the program step number are read out to the adder circuit 17, where they are subtracted by "-1" to become "255" and returned to the Xu area of the X register 19. It will be done. In operation step S6, the judgment circuit 37 judges whether or not there is a numerical code in the Xu area of the Return to step 2. In operation step S2, the contents "0, 2" of the address register 34 are output from the upper and lower registers 35, 36, respectively, and the contents of the address "0, 2" of the program register 25, that is, the third As shown in the figure, "0, ENT" is read out and transferred to the instruction register 23, and the presence or absence of stored data is determined by the determination circuit 37 in the same manner as described above. Thereafter, as described above, the AT V register 34 is incremented by one step, the contents of the Xu area of the X register 19 are decremented by 1, and the contents of the address are transferred from the program memory 25 to the instruction register 23. The determination circuit 37 determines whether or not there is stored data.

For example, when the contents of the upper and lower registers 35 and 36 become "1, 14", "0, END" read from the program memory 25 is put into the instruction register 23, and the judgment circuit 37 inputs the stored data. At this time, since there is stored data, the result of the determination is "YES". Thus, the address advances one more step, and the upper and lower registers 35 and 36
becomes “2,0”, the program memory 25 “2,
The content "0,0" of the address "0" is transferred to the instruction register 23, but the judgment result in the operation step S is "NO" because there is no stored data at the moment, and the ROM address section 2 is transferred to the instruction register 23. Zip up to the address for display. At this time, "240", which is the number of steps used in program 1 subtracted from the maximum number of steps, is stored in the Xu area of the X register 19.
By the output from the ROM 3 addressed to the OM address section 2, the above “240” is converted to the serial/parallel conversion circuit 38.
and is displayed on the Xu area of the display device 40 via the decoder 39 as shown in FIG. 5q. On the lower side of the triangle, a "P" is displayed to indicate that the program instruction (Pr) key has been operated, as in the case of program 1. Therefore, the operator knows that the remaining storage capacity of the program memory 25 is [240] steps, and can judge whether or not this program 2 can be written. Note that the operation step S6 is determined to be "NO" when there is no numerical code in the Xu area of the display register 19, that is, when the maximum program step [256 '' has been completed and there are no remaining steps, and ``0'' is displayed on the display device 40.

As described above, according to the present invention, in a small electronic computer with a program that can store multiple programs, it is possible to write a program by simply operating the program instruction key that is operated first when writing a program. The unmemorized capacity can be detected by calculating the remaining program steps, so written programs are not wasted. It has various advantages such as being able to use the program storage area effectively by easily calculating and displaying the calculations.

[Brief explanation of drawings]

(Fig. 1 is a block diagram of a block circuit for explaining the outline of this invention, Fig. 2 is a block diagram of a block circuit showing an embodiment of this invention, and Fig. 3 is a block diagram of a program memory according to the embodiment. FIG. 4 is a flowchart illustrating the operation of the same embodiment, and FIG. 5 is a diagram showing the relationship between the progress of program steps and display examples on the display device. 1... Key input section, 19... Arithmetic register, 25...
...Program memory, 34...Address register,
, 37... Judgment circuit.

Claims (1)

[Claims] 1 Key input means including at least program-related keys and a specific key for specifying the type of program; a program storage section into which a plurality of programs are written by operating the program keys during a program write mode; and a program write mode. A detecting means for detecting a first address in the program storage section to which no program is written by operating the specific key in the program storage section, and a means for calculating remaining program steps based on a detection output from the detecting means. A program step calculation method featuring the following.