JPS6019030B2 - educational electronics - Google Patents

Description

[Detailed description of the invention] The present invention relates to a small electronic computer.

Conventional portable electronic computers aim to enable any young or unskilled person to perform calculations such as addition, subtraction, multiplication, and division by simple operations to obtain the results. FIG. 1 is a perspective view showing an example of a conventional small electronic calculator.

a is a group of numeric keys for entering numbers from 0 to 9 and the decimal point,
b is a group of function keys for instructing commands and command execution. By operating the function key group b, operations such as four arithmetic operations on the operands and operands input by operating the numerical key group a are performed. For example, if you want a computer to calculate 123×24, key operations are performed in the following order.

m→figure→figure→figure→figure→fourth→eye By operating the above keys, the display device displays the layer number calculation result as shown in FIG.

Therefore, calculation results are obtained with a so-called one-touch operation (with a small number of operations), and it is impossible to understand the progress of the calculation, that is, the details of the calculation method, and it is not recommended for use by elementary school students, junior high school students, etc. from an educational standpoint.

An object of the present invention is to provide an educational electronic device that eliminates the above-mentioned educational disadvantages and brings about educational effects.

A further object of the present invention is to provide an educational electronic device that provides an excellent educational effect for learning the process of division.

FIG. 3 is a block diagram showing an embodiment of the educational electronic device according to the present invention.

KI is a keyboard input device for inputting data into a computer; for example, as shown in the figure, there are a group of numeric keys NK for inputting 0 to 9 and a decimal point into the computer, a group of function keys for giving instructions for four arithmetic operations, instruction execution, and instructions for clearing memory contents. FK
, a changeover switch MS for switching calculation modes, a quotient key QK used in division calculations, a remainder key RK, and a decimal point setting dial DP.

The control circuit CU detects the operation of keys on the keyboard input device KI, outputs numerical signals and control signals corresponding to the keys, and also detects the states of other circuits and outputs other control signals.

FIG. 4 is a block diagram showing a display control section of the control circuit CU shown in FIG. 3.

In the figure, SWI is a switch that is opened and closed by the operation of the quotient key QK shown in FIG. 3, and SW2 is the remainder key RK.
This is a switch that opens and closes by operating the switch. switch SW
1 and SW2 are flip-flops FF1 and FF, respectively.
Set 2.

SW3 is a switch that informs the computer of two states when the selector switch MS shown in FIG. 3 is operated. By switching the switch SW3, the voltage V
When DD is applied to the first control circuit CU1, the first control circuit CU1 is informed to perform the learning mode, and vice versa, to perform the same processing as a normal computer.

Furthermore, the first control circuit CUl has a flip-flop FF1.
, FF2's Q1 and Q2 are applied, and a signal for opening and closing AND gates AG4 and AG5 is output.

The output of the flip-flop FF2 is also applied to the remainder signal generating circuit RSG, and the output of the remainder signal generating circuit RSG is supplied to the display device.

QSG is a quotient signal generating circuit that detects the contents of register C obtained through AND gate AG4 and applies a quotient signal to display device DP.

DPSG is a decimal point position generator that inputs the decimal point information set by the decimal point dial DPS.The output of the decimal point position generator DPSG is sent to the coincidence circuit CC via the switch SW4 of the decimal point dial DPS, compared to the output.

When such an output from the coincidence circuit CC is obtained, the termination signal generator ESG sends an termination signal des to the display device DP to light up a display body to be described later. The OR gate OGI sends code signals corresponding to each key of the numerical key group NK of the key input device KI to the AND gates AG1 and AC via the control circuit CU.
2. The numerical data applied to AG3 and passed through the arithmetic circuit ALU is also applied to one end of the input of the AND gates AGI to AG3, and is sent to the registers RA and RB via the AND gates opened by the control signal of the control circuit CU. , RC. Each of the above registers RA, RB, R
The output of C is sent to the arithmetic circuit ALU, and under the control of the control circuit CU, the data in the register is determined by gate control as is known in the art, processed by an adder/subtractor (not shown), and stored in registers R and R.
Input to B and RC.

AND gates AG4 and AG5 are gates that send the contents of registers RC and RA to the display device DP.
The signal qSI of the first control circuit CU1 is applied to the AND gate AG5, and the signal rSI of the first control circuit CU1 and the output signal 2 of the flip-flop FF2 are applied to the AND gate AG5.

The data passing through the AND gates AG4 and AG5 is input to the display device DP via the OR gate OG2 and displayed.

The display unit of the display device DP, for example, as shown in FIG. , DD2, DD3.

For example, the display DDI represents the quotient, the display DD2 represents the remainder, and the display D03 represents the end of calculation. The above display bodies ND, MD1,
MD2 and MD3 are displayed by matching driving of the digit signal DS and the information signal CS from the decoder driver DD. The operation of the embodiment configured as described above is as follows: 123000÷7
= Explain with a calculation example.

First, the cut-off switch MS is operated and set to the right side as shown in the figure, and as shown in the fourth figure, an H level (VDo) signal is applied to the first control circuit CU1, informing the computer that it is in the learning mode. .

Next, the decimal point dial DPS is operated to set the number of digits below the decimal point, and for example, as shown in the figure, one digit below the decimal point is set. Next, the numeric key group NK is operated, and 1230
Data of 00 is input to the register RB, and the control circuit CU
The display control signal is sent to the display device DP via the AND gate AG6, and the dividend data is displayed.

Next, when the "÷" function key FK, which instructs division, is operated, the result is determined by the control circuit CU and stored in a storage means (not shown), such as a flip-flop. Next, when the divisor data 7 is input, the multiplicand data is
A, the divisor data 7 is input to the register RB, and as described above, it is sent to the display device DP via the AND gate AG6 and displayed.

Next, when the quotient key QK is operated once, it is first detected that the quotient key QK has been operated, and then, although not shown in Fig. 6, it is detected whether the quotient key QK has been operated for the first time or not. .

Is it possible to perform such detection by setting a flip-flop or the like according to the operation of the commercial key QK and detecting the set state?

As a result of such detection, if it is the first time, registers RA and RB
The data in [ is shifted to the left and its most significant number matches the highest digit of the register. Next, the data in register RA and the data in register RB are compared in magnitude by the arithmetic circuit ALU, such as RA-RB→RA. Check the size with the data of RB, and after checking R
Perform the calculation A+RB→RA based on the state of numerical data.

If the result of the comparison between the data in register RA and the data in register RB is RA<RB, then register RB
The contents of are shifted one place to the right.

Next begins division, which is performed by repeating subtraction. First, the data in register RA and the data in register RB are compared in size as described above. Such result RA>R
If it is B, the calculation RA-RB→RA is performed via the calculation circuit ALU, and further calculation is performed to add 11 to the register RC. The above-described control procedure of comparing the data in register RA with the data in register RB and causing register RC to increase by 11 is repeated until the data in register RA becomes smaller than the data in register RB.

At the end of such an iteration, a single digit quotient is obtained.

Therefore, in response to the H level signal of the flip-flop FFI set by the operation of the quotient key, the quotient signal generating circuit Q
SG outputs a 100% signal to the signal line dsame, and uses this quotient signal to display the display MDI on the display device DP. In this display example, a circle mark is used, but the format is 8
A special pattern may also be formed using square-shaped segments. Further, the H level output of the flip-flop FFI is applied to the AND gate AG5 via the signal line rS2, and the quotient data (in this case MI) stored in the register RC is sent to the display device DP, and the quotient data stored in the register RC is sent to the display device DP. Is displayed.

Next, one of the signals output from the multiple output terminals of the decimal point position generator DPSG according to the settings of the 4-point dial D is applied to the coincidence circuit CC, and then applied to the other input terminal of the coincidence circuit CC. A comparison is made with the output of the decimal point counter DDC, and since there is still no data below the decimal point in the quotient data stored in the register RC, the calculator resets the flip-flop FFI and returns to the key sense state.

Next, when the remainder key RK is operated, the switch SW2 is closed, the flip-flop FF2 is set by applying the voltage VDD, and the remainder key R is operated by the first control circuit CUl.
It is determined that K has been operated, and a signal for displaying the remaining data stored in the register RA is output from the signal line 1 of the first control circuit CUl, and the AND gate AG
5 and one input terminal of the flip-flop F.
The output of F2 is also applied to its input terminal, and the remaining data in register RA is sent to display device DP via AND gate AG5.
and is displayed as shown in FIG.

Furthermore, the output of the flip-flop FF2 is detected, and the remainder signal generating circuit RSG outputs a signal to the signal line d, and the display body M
D2 is displayed to indicate that the numerical value displayed on the display body ND is a remainder. Next, the output of the decimal point counter DDC and the decimal point position generation circuit selected by the 4/number dial DPS determine the number of digits below the decimal point in the data in the register RA, that is, whether or not it satisfies the value set by the decimal point dial DPS. Comparison circuit C with the DPSG signal
If they do not match, the flip-flop FF2 is reset by a control means (not shown) to enter the key sense state.

Next, when the quotient key QK is operated, it operates as described above,
First, the contents of register RC are shifted to the left by one digit, and the quotient key QK is
The first control circuit CUl indicates that has already been operated once.
register R by examining storage means (not shown) in
Control is performed to compare the magnitude of the data of A and the data of register RBO, and a one-digit quotient is obtained as described above, and the 1 obtained last time and the "7" bound this time are displayed in the register RC on the display device DP.
is displayed. Thereafter, each time the quotient key QK is operated, the displayed cocoon data increases by one digit, such as "175" and "1757", and the display MDI is also displayed at the same time. Next, when the remainder key RK is operated, the calculator operates as described above, and "10" is displayed along with the ○ mark on the status display MD2.Next, the quotient key QK is pressed twice in succession. When operated, “175” appears on the display device DP in response to the key operation.
71" and "17571.4" are displayed, and when the latter key operation is performed, the comparator circuit CC determines that the output of the 4-point counter DDC matches the decimal point position information selected by the decimal point dial D. The completion signal generating circuit ESG, which indicates that the division operation has been completed, generates the signal de.
s is generated, the display MD3 is lit, and the operator is notified of the completion of the calculation.

When the remainder key RK is further operated, the remainder data in the register RA is displayed as described above, and the decimal point is checked for coincidence as described above, and the display MD3 is displayed again to inform the operator that the calculation has ended. be done.

In the above embodiment, mode selection was performed using a switching key, but it may be configured in the same manner as a numeric key and operated each time a calculation is performed.

As described above, the present invention includes an arithmetic instruction means that is operated multiple times to obtain the division result so that the division result is not obtained all at once, an instruction means that is operated to obtain the remainder of the division,
The apparatus is configured to increase and display the number of digits to be displayed in the result of the division each time the calculation instruction means is operated, and to display the remainder of the division in response to the operation of the instruction means. Because of this, it is extremely effective in learning the process of calculations.

[Brief explanation of the drawing]

Fig. 1 is a perspective view of a conventional educational electronic device, Fig. 2 is a diagram illustrating an operation example of the educational electronic device shown in Fig. 1, and Fig. 3
The figure is a block diagram of an educational electronic device according to the present invention, FIG. 4 is a block diagram showing in more detail the control portion of the control circuit CU shown in FIG. 3 according to the present invention, and FIG. FIG. 6 is a control diagram illustrating the operation of the embodiment of the present invention, and FIG. 7 is a diagram illustrating an example of a display in response to a key operation. QK is a fill key, RK is a remainder key, CU1 is a first control circuit, and AGI to AG6 are AND gates. Sora's four Tsutomu z8 inferior 5 drawing 3 drawing 49 grandchild 6 drawing Tsutomu wa drawing

Claims (1)

[Claims] 1. An arithmetic instruction means that is operated multiple times to obtain the result of division; an instruction means that is operated to obtain the remainder of the division; and an instruction means that indicates the number of digits to be displayed in the result of the division each time the arithmetic instruction means is operated. and means for displaying the remainder of the division in response to the operation of the indicating means.