JPS6146856B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a small electronic calculator capable of combinatorial calculations. Recently, in the field of small electronic calculators, such as electronic desktop calculators, with the spread of these devices, there is a trend toward smaller and thinner devices, as well as higher functionality.
In addition to various arithmetic functions such as trigonometric functions, exponential functions, logarithmic functions, and factorial operations, computers that can also perform permutation operations (nPr) and combination operations (nCr) have been put into practical use. On the other hand, in the case of conventional computers of this type, combinatorial calculations have been (However, n and r are both positive integers) When calculating, it was necessary to use the same subroutines as much as possible, avoid adding unnecessary steps and associated complicated circuits, and reduce the size of the circuit. Therefore, conventionally, when calculating a combinational operation, a calculation method was used in which a subroutine for performing a factorial calculation, which was originally provided in a computer, was used as is. That is, in the above formula, first
Calculate n1, then calculate the denominator r1 and (n-r)1, then calculate r1x(n-r)1, and finally divide the above n1 by r1x(n-r)1. method was used. However, for example, the number of digits displayed in the mantissa and the number of digits displayed in the exponent are 9 digits and 3 digits, respectively, and the range that can be displayed (that is, the range that can be calculated) is -9.9999999.
×10 ⁹⁹ ~ 9.9999999 × 10 ⁹⁹ If you use the above calculation method on a computer and try to calculate a combination operation, if you input numbers n and r of 70 or more, n1 or n1 of the numerator when executing the combination operation nCr While calculating the denominator r1, the intermediate result becomes a value larger than the number of digits that can be displayed, causing an overflow and making calculation impossible. However, for example, the number n=80, r
When trying to execute the combinational operation ₈₀ C ₇₈ with =78 as the input value, the result is 3160 and even though this can be displayed, an overflow occurs during the factorial operation 801, and the above combinational operation cannot be performed. The problem was that no results were obtained. That is, the range of input data that can be calculated is limited to an extremely narrow range, and it is not possible to calculate all combinational operations whose answers can be displayed. On the other hand, the above combinational operation is nCr=n ^C (n
-r), in the magnitude relationship of the numerical value r (n-r), (i) When r≧n-r, nCr=n・(n-1)...(r+1)/(n-r)
! ...(2) (ii) When r<n-r, nCr=n・(n-1)...(n-r+1)/r! …
...(3). The present invention has been made in view of the above circumstances, and by using factorial operations and adding a simple judgment means, it is possible to calculate all combinations of results that can be displayed, and to improve the calculation speed. The object of the present invention is to provide a small electronic calculator that has a combinatorial calculation function that can measure. Hereinafter, one embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a circuit block diagram showing one embodiment of the present invention, and numeral 11 in the figure is a ROM in which various microinstructions are stored. Then, from the ROM 11, a signal S _U which specifies the row address of the register storing the operands stored in RAM 12, which is a memory for calculations described later, and a signal specifying the row address of the register storing the operands are sent. F _U , a signal S _L specifying the column address of the register storing the operand or the processing start column address; and a signal F _L specifying the column address of the register storing the operand or the processing end column address. , a numeric code signal C ₀ that outputs a numeric code necessary for calculation and judgment steps, an operation code OP such as an arithmetic instruction, a numeric code generation instruction, and a transfer instruction, and a signal Na that designates its own next address are connected to the bus line a. ~g is output in parallel. The signal Na output via the bus line g is
The contents of the ROM 11 are temporarily stored in an address register 13 that specifies the address where the contents are stored. The output of the address register 13 is input to the ROM address section 14. This ROM address section 1
4 decodes the signal input from the address register 13 and selects and specifies the address of the ROM 11. Further, the operation code Op is supplied to the operation decoder 15 via the bus line f. This operation decoder 15 is
Decode the above operation code Op to read out, for example, the data output command OF of the register specified by the row designation address F _U , the data output command OS of the register designated by the row designation address Su, the key input read command KE, and the indirect address read. Command
Outputs various control commands such as ID, subtraction command SB, specified digit length mode M, and change command JU. Also,
A control command is sent from the operation decoder 15 to the timing recorder 16. This timing decoder 16 is an operation decoder 1
Various timing signals φa are generated in accordance with the above control commands from 5, specified digit length mode M, and clock pulses φ ₁ , φ ₂ and timing pulses t ₁ to _{t 3} shown in FIG. 2 given from a timing pulse generator (not shown). ~φd, ta~tc, code input command CI, read/write command R/W, etc. are output. The above timing signals are φa=t ₃・φ ₁・OP ₁ φb=t ₂・φ ₁・OP ₁ φd=t ₃・φ ₁・+Bφ ₁ ta=・S _T +M・t ₁ tb=M・₁ tc =・_T. In Figure 2, t ₁ to _{t 3} correspond to one digit, and when reading data from the RAM 12, the contents of the register addressed by Su are read at the timing of t ₁ , and the contents of the register addressed by Fu are read out at the timing of t 1. The contents of the register addressed by Fu are read at timing t ₁ , the contents of the register addressed by Fu are read at timing t ₂ , and when writing, the contents of the register addressed by Fu are read at timing t ₃ . It is written at the timing of Further, the timing signal _OP1 is a display and key sampling command from the operation decoder 15, and ST is a start command for the next step, which is supplied from the flip-flop 17 to the timing decoder 16 at the beginning of the command step.
Further, the designated digit length mode M is "1" if the RAM 12 designation is one digit, and "0" if it is two or more digits. The row designation address signals S _U and F _U output from the ROM 11 are applied to the gate circuits G ₁ and G ₂ via the bus lines a and b, respectively, and
The outputs of these gate circuits G ₁ and G ₂ are sent to the row address input terminal RAU of the RAM 12 via the bus line h.
Enter. The gate circuit G ₁ is directly supplied with the timing signal t ₁ shown in FIG. 2, which is output from a timing signal generation section (not shown), and
A timing signal t ₁ is supplied to the gate circuit G ₂ via an inverter 18 to control opening and closing of the gate. Also, RAM1 output from ROM11
The column address or processing start column designation address signal S _L and the column address or processing end column designation address signal F _L of 2 are applied to gate circuits G ₃ and G ₄ via bus lines c and d, respectively. The gate circuits G ₃ and G ₄ are gate-controlled by timing signals ta and tb' outputted from the timing decoder 16, respectively. And the above gate circuit
The outputs of G ₃ and G ₄ are output to the input/output bus line 1 and input to the column address input terminal RAL of the RAM 12. Further, the output of the gate circuit G ₃ is supplied to the counter 20 . This counter 20 performs a counting operation in response to a timing signal φd, and counts up by one each time the timing signal φd is input. Then, the counter 20
The output of is applied to the column address input terminal RAL of the RAM 12 via the gate circuit G ₅ and also applied to one input terminal of the matching circuit 21. The other input terminal of the matching circuit 21 is supplied with a processing end column designation address signal F _L outputted from the ROM 11 to the bus line d. The specified digit length mode M output from the operation decoder 15 is applied to this matching circuit 21 via an inverter 22, so that the matching circuit 21 operates when the output of this inverter 22 is "1". It's summery. The coincidence output of this coincidence circuit 21 is applied to an AND circuit 23 and is also inputted to a flip-flop 17 via an OR circuit 24. Furthermore, the specified digit length mode M output from the operation decoder 15 is applied to the flip-flop 17 via an OR circuit 24. This flip-flop 17 reads an input signal in synchronization with the timing signal _t3 · _φ1 , and outputs the above-mentioned start command ST in synchronization with the next timing signal _t1 . Further, the specified digit length mode M output from the operation decoder 15 is applied to the AND circuit 25. Timing signals t ₃ and φ ₁ are input to AND circuits 23 and 25, and their output signals are sent to address register 13 via OR circuit 26 as read clock signal e. On the other hand, the RAM 12 has registers with 16 digits (0 to 15 digits) as shown in FIG.
Five registers Y, Z, A, and B are provided in the row direction, and the 0th to 1st digits of each register are exponent data, the 2nd digit is code data indicating the positive or negative of the exponent data, and 3. The 13th digit stores mantissa data, the 14th digit stores flag data that stores the type of operation or control, and the 15th digit stores sign data that indicates whether the mantissa data is positive or negative. Ru. Each of the registers X, Y, Z, A, and B is assigned a row address number (1) to (5), and each register is assigned the address number by the row designation address signal Fu or Su. The address is specified when the code corresponding to is output. Also, the digits of each register above
15 is designated by the column designation address signal F _L or S _L . Further, reading and writing of data in each of the registers of the RAM 12 is controlled by the R/W signal output from the timing decoder 16, and when this signal is "0", a read operation is performed; ”, the write operation is performed. Therefore, the address is specified by the row and column address signals mentioned above, and after the operation, the RAM 12 outputs the address at a predetermined timing t ₁ for the operand, transfer, etc.
The data read at and t ₂ is output at the output terminal OUT
_The data is output as parallel 4-bit data, and sent to the latch circuit 27 via the gate circuit _G6 , which is gate-controlled by the timing signals t ₁ and φ 1, and is also gate-controlled by the timing signals t ₂ and φ _1. It is sent to the latch circuit 28 via _G7 .
The output of the latch circuit 27 is input to the column address input terminal RAL of the RAM 12 via a gate circuit _G8 controlled by the indirect address read command ID output from the operation decoder 15. Furthermore, the output of the latch circuit 27 is supplied to the input terminal a of the arithmetic circuit 29 via a gate circuit _G9 controlled by the data output command OS output from the operation decoder 15. Further, the data outputted from the latch circuit 28 via the gate circuit _G10 is sent to the input terminal b of the arithmetic circuit 29 and also to the buffer 30. This buffer 30 operates in synchronization with the timing signal φa, and its output is sent via a decoder 31 to a display section 32 for display. The arithmetic circuit 29 is equipped with an arithmetic data output line j and a carry output line k, and the data output from the line j is input to the input terminal IN of the RAM 12 and sent to the AND circuit via the OR circuit 33. 34
It can also be added to. Further, a carry or borrow signal outputted to line k is applied to an AND circuit 35. The AND circuits 34 and 35 output signals when the operation decoder 15 gives a judge command JU, and the AND circuit 3
The outputs of 4 and 35 are input to the address register 13 as address data for the branch step. Further, from the latch circuit 27 to the gate circuit
The data output via _G9 is input to the buffer 36 which operates in synchronization with the timing signal φb. The output of the buffer 36 is sent to the key input section 38 as a key sampling signal via a decoder 37, and is also sent to the display section 32 as a display digit selection signal (digit signal). The key input data outputted from the key input unit 38 is stored in a buffer 39 that operates in synchronization with the timing signal _t3 · _φ1 , and is sent to a gate controlled by the key input command KE outputted from the operation decoder 15. Arithmetic circuit 3 via circuit G ₁₁
It is input to input terminal a of 0. Further, the numerical code _C0 outputted from the ROM 11 to the line e is inputted to this input terminal a via the gate circuit _G12 . This game circuit _G12 is controlled by the code input command CI output from the operation decoder 15. Next, according to FIG. 4, the address register 13,
Details of the ROM address section 14, ROM 11, operation decoder 15, and timing decoder 16 will be explained. It should be noted that FIG. 4 shows only the parts related to the processing when the nCr key is operated for each of the above-mentioned circuit parts, and other parts are omitted. Address register 13 is n
Of the bit configuration, the lower 15 bits are shown, and the next 5-bit address Na output from the ROM 11 is input to each bit. In this case, the outputs of the AND circuits 34 and 35 are input to the first and second bits of the address register 13 via the OR circuits 41 and 42 together with the next address Na. Each bit output of the address register 13 is sent to the ROM directly and via an inverter.
It is sent to the address section 14, where it is decoded.
Specify the address of ROM11. ROM11 is
For example, S _U , F _U , S _L , F _L , C _O , Op, Na
Outputs signals such as In this case, the row designation address signals S _U and F _U are output as 3-bit codes, the column designation address signals S _L , F _L and the code signal C _O are output as 4-bit codes, and the operation signal OP and the next address signal Na are output as 5-bit codes. The operation decoder 15 decodes the operation code OP output from the ROM 11 and outputs control commands such as SB, JU, M, OS, OF, etc. The timing decoder 16 forms an AND circuit with various timing signals according to the control signal output from the operation decoder 15, and outputs φd,
Control signals such as CI and R/W are output in synchronization with the timing signal. That is, the timing signal φd is output in synchronization with the timing signal t _{3 1} when the specified digit length command signal M is not output from the operation decoder 15, and the code input command signal CI is output from the line l of the operation decoder 15. ₁
Start signal ST when signal “1” is output to
output in sync with The read/write command signal R/W is output as a "1" signal in synchronization with timing _t3 when the signal "1" is output on line _l2 of the operation decoder 15. At this time, the RAM 112 is in write mode, and the others are in read mode. Note that descriptions of other timing signals shown in FIG. 1 output from the timing decoder 16 are omitted here. FIG. 5 shows the relationship between the operation code OP for the main operations and each control signal output at that time. Further, FIG. 6 is a diagram showing the relationship between the addresses selected for execution of each step and the main various control signals output at that time. Next, the operation of the present invention configured as described above will be explained with reference to the flowcharts of FIGS. 7 and 8 and the storage state diagram of X, Y, A, and B shown in FIG. 9. Now, taking the calculation example: ₁₂ C ₇ = 792 ...(4) as an example, use the key input section 38 to enter □1□2 (first numerical value n) ₁₂ C ₇ □7 (second numerical value r)□= A key operation is performed and the input data is stored in registers X, Y, A, B.
As shown in Figure 9a, X=12, Y=5, A=0, B=
The explanation will start from the point in time when each 0 is stored and the combinatorial operation of the above equation (4) is started inside the computer. In addition, in Figure 9, the decimal position between the 12th and 11th digits of each register is fixed for the display, and the last two digits of the exponent part (0 and 1
digit) represents the power digit of 10, the third digit of the exponent part represents the sign of the power (“1” represents “+”, “0” represents “-”, and the 15th digit represents the significand of the mantissa ( "0" represents "+" and "1" represents "-").For example, the contents of the X register in Figure 9a are
1.200000000 10 means ¹ and represents the number 12. Further, the symbol "F" in the 14th digit of the X register in the same figure is a combination operation code, and when the combination operation key ncr is operated in the key input unit 38, it is written in the 14th digit according to a predetermined control. It is something. When the key operations are performed as described above, the state of each register becomes _a as shown in FIG.
An operation is performed to transfer the A register to the A register. In this step S _A , the address register 13 sends the ROM 11 through the ROM address section 14.
The address is addressed, and "0100" (binary number) is output from the ROM 11 as the operation code Op. This operation code Op is decoded by the operation decoder 15 shown in FIG. 4, and the signal OS becomes "1". At this time, the signal R/W is output from the timing decoder 16 in synchronization with the timing signal _t3 . be done. At this time, ROM11
The row designation address signal Su output from is "001"
(1), Fu is output as "100" (4), column address signal S _L is output as "0000" (0), and F _L is output as "1111" (15).
Therefore, at timing _t1 , which is one cycle of the first digit of this step, the above signal
Su(1) passes through the gate circuit _G1 , and the signal S _L (0)
is the gate circuit G ₃ (at this time, the signal M is from “0” to ta=
ST+M・t ₁ is “t”) respectively RAM1
2 terminal RAU and terminal RAL, RAM
The 0th digit of the X register in 12 is specified. As a result, the content "1" in the 0th digit of the X register is read out and set to the latch circuit 27 via the gate circuit _G6 at the timing of _t1 · _φ1 . At this time the signal
Since OP is “1”, the contents set in the latch circuit 27 are sent to the arithmetic circuit 2 via the gate circuit _G9 .
9 will be input. Also, at this time, the content (0) of the signal S _L is set in the counter 20. Next, at timing t ₂ , nothing is done,
Next, at timing _t3 , the RAM 12 is designated with the 0th digit of the A register by the signal F _U (4) and the above-mentioned signal S _L (0), and the above-mentioned R/W
When the signal becomes "1", the mode changes from the read mode to the write mode. Therefore, the content "1" in the 0th digit of the X register set in the latch circuit 27 is written to the 0th digit of the A register from the input terminal IN of the RAM 12 via the gate circuit G ₉ and the arithmetic circuit 29. At this time, the contents of the counter 20 are incremented by 1 by the timing signal b output by the timing decoder 16, and the value becomes "1".
becomes. Moreover, the above S _L signal (0) and the signal F _L
(15) is supplied to a signal-operated matching circuit 21 and compared to see if there is a match. Since no coincidence signal is output here, the AND circuit 23 is not opened. On the other hand, in this step, since the signal M is not output from the operation decoder 15, the AND circuit 25 is not opened either. Therefore, OR circuit 2
From 6 onwards, the read clock e is not output, and the next digit cycle _t1 to _t3 is entered without updating the contents of the address register 13. In this cycle, the contents of the first digit of the X register are transferred to the first digit of the A register. First, at timing _t1 , the signal S _U (0) is supplied to the RAM 12 via the gate circuit G ₁ to specify the X register, and the column address signal is supplied to the RAM ₁₂ via the gate circuit G ₁ . (Not available)
Instead, the content 1 of the counter 20 is supplied to the RAL terminal of the RAM 12 via the gate circuit _G5 opened by the timing signal t, and the first digit is designated. By this address designation, the content "0" of the first digit of the X register is read out and set in the latch circuit 27. Then, by the same operation as described above, the contents set in the latch circuit 27 are written to the first digit of the A register in the RAM 12 at timing _t3 . Furthermore, since the output of the gate circuit _G5 is also applied to the input side of the counter 20 and the coincidence circuit 21, at the timing of _t3 , the content of the counter 20 is again incremented by 1 by the timing signal _φ0 and becomes "2". '', and the coincidence circuit 21 compares the coincidence with the signal F _L (15). Since there is no match at this time, no match signal is obtained from the match circuit 21, and the address contents of the address register 13 are not updated in the same way as described above, and the next digit cycle begins.
In this way, the operation of sequentially transferring the contents of each of the 0 to 15 digits of the X register to the corresponding digit of the A register while specifying the column address by the counter 20 is repeated. When the content of the counter 20 becomes "15", the content of the 15th digit of the X register is transferred to the 15th digit of the A register at timing _t3 . At the same time, the matching circuit 21 finds a match between the content "15" of the counter 20 and the signal F _L (15), and outputs a matching signal. This coincidence signal is applied to the flip-flop 17 via the OR circuit 24, and read at the timing _t3 · _φ1 . Then, the start signal is synchronized with clock pulse ₂ .
ST is output and given to the timing decoder 16. Therefore, the start signal ST will be output in the first digit cycle of the next processing step. Further, the coincidence signal is applied to the address register ₁₃ as a read clock pulse e through the AND circuit 23 and the OR circuit 26 in synchronization with the timing _t3.1 , and the contents of the address register 13 are changed. At this time, since the signal J _U is not output from the operation decoder 15, the address signal given to the address register 13 is only the next address signal Na ("11110"(30)") output from the ROM 11. Yes, the contents of the address are changed to (30) and the process advances to the next step S _B. Next, in step S _B , the contents of the Y register are changed to "7".
An operation is performed to transfer the data to the B register. In this step S _B , address 30 of the ROM 11 is addressed, and the ROM 11 outputs "0100" (see FIG. 6) as the operation code Op. With the output of this operation code Op, the signal OS from the operation coder 15 becomes "1",
At this time, the timing decoder 16 outputs the signal R/
W is output in synchronization with the timing signal _t3 (see Figure 5). At this time, the row designation address signal S _U output from the ROM 11 is "010" (2), F _U is "101" (5),
Column address signal S _L is “0000” (0), F _{L is} “1111”
(15) is output. Then, under the control of these signals, an operation similar to step S _A is executed,
The content "7" of the Y register is transferred to the B register. When this operation is completed, the next address signal Na output from the ROM11 at this time is "00010" (2)
Therefore, the address contents are changed to (2) and the process proceeds to the next step Sc. The state of each register at that time is as shown in FIG. 9b. Next, in step Sc, the contents of the A register are "12".
Then, the content "7" of the Y register is subtracted and the result is written to the A register. That is, an operation of calculating a numerical value (nr) and writing it into the A register is executed. In this step Sc
Address 2 of the ROM 11 is addressed, and "0101" is output as the operation code Op.
(See Figure 6) When performing this subtraction operation, in reality, a step is first performed to match the decimal point positions of the contents of the A register and the contents of the Y register, and the contents of the mantissa part of the A register are one digit. At the same time, the contents of the exponent part become "100". That is, the mantissa contents of the Y register and A register are

[Table] However, the explanation of the instruction state diagram and operation in the ROM 11 of that step will be omitted here. Then, the instruction for the next subtraction operation is shown. As mentioned above, when the operation code OP "0101" is output from the ROM 11, the operation decoder 15 outputs the subtraction signal SB and the control signal OS.
and OF are output, and timing decoder 1
From 6 onwards, a read/write signal R/W is output in synchronization with the timing signal _t3 . At this time, ROM1
The row designation address signal S _U output from 1 is "010" (2), the F _U is "100" (4), and the column address signal S _L
"0011" (3) is output for F _L "1101" (13).
At this time, the signal M is "0" and is "1".
Therefore, at the timing _t1 of the first digit cycle of this step, the above signal S _U (2)
is passed through the gate circuit _G1 , and the signal S _L (3) is passed through the gate circuit _G3 , which is opened at the timing of ta.
It is supplied to the terminals RAU and RAL of the RAM 12, and the third digit of the Y register in the RAM 12 is designated. Then, the signal R/W of RAM12 is “0”
A signal or readout signal is provided. As a result, the content of the third digit of the Y register "0" can be read,
It is set to _the latch circuit 27 via the gate circuit _G6 at the timing of _t1.1 . At this time, the signal OS
Since it is "1", it is applied to the a terminal of the arithmetic circuit ₂₉ via the latch circuit G9. Also, at this time, the content (3) of the signal S _L is set in the counter 20. Next, at timing _t2 , the gate circuit _G1 is closed and the gate circuit _G2 is opened, so the row address signal F _U (4) is supplied to the RAU terminal of the RAM 12, and the column address signal S _L (3) is supplied to the RAU terminal of the RAM 12. It is subsequently supplied to the RAL terminal via gate circuit _G3 , and the third digit of the A register is designated. As a result, the contents of the third digit of the A register are read out from the OUT terminal of the RAM 12, and set in the latch circuit 28 via the gate circuit _G7 at timing _t2 · ₁ . At this time, since the signal OF is "1", the contents set in the latch circuit 28 are applied to the b terminal of the arithmetic circuit 29. Next, at timing t ₃ , the row address signal and column address signal to the RAM 12 are the same as the timing at t ₂ , and the third digit of the A register is specified, but the R/W signal is sent to the timing decoder at this timing. "1" is supplied from 16, and the write mode is entered. In response to the subtraction signal SB from the operation decoder 15, the arithmetic circuit 29 subtracts the contents of the third digit of the Y register from the contents of the third digit of the A register read out from the RAM 12, that is, "0-0. '' is performed, and the result is written to the third digit of the A register from the IN terminal of the RAM 12 via the pass line j. At this time, the contents of the counter 20 are determined by the timing signal D output from the timing decoder 16, and its value becomes "4". The S _L signal (3) and the signal F _L (15) are also supplied to a signal-operated matching circuit 21 for comparison. However, no match is obtained here, and no match signal is obtained from the match circuit 21. Therefore, step SA
With the same operation, the address contents of the address register 13 are not changed and the next digit cycle t ₁ ~
Enter _t3 . Here again, the operation is the same as in step SA except that subtraction is performed as an operation in the arithmetic circuit 29.
The contents of the fourth digit of the register are subtracted (0-0), and as a result, "0" is written to the fourth digit of the A register. Similarly, each digit cycle is repeated and subtraction is performed for each digit up to the 13th digit. As a result, AY = "12-7", that is, the numerical value "5" is stored in the A register, resulting in the register state as shown in FIG. 9c. In the cycle in which subtraction is performed up to the 13th row between both registers, the match circuit 21 outputs a match signal. This match signal is applied to the flip-flop 17 via the OR circuit 24 in the same manner as in step S _A , and outputs the start signal ST, and is read into the address register 13 via the AND circuit 23 and the OR circuit 26 and is applied as a clock pulse e. It will be done. At this time, the only address signal given to the address register 13 is the next address signal Ne ["00011" (3)] output from the ROM 11, and the content of that address is changed to (3), and the step S Proceed to _D. At this time, the status of each register becomes as shown in FIG. 9c. In the next step S _D, the contents of the Y register (second
The magnitude relationship between the numerical value r) and the contents of the A register (the numerical value n−r) is determined. That is, in this step, if r≧n−r, preparations are made to execute the calculation based on the above equation (2), and on the other hand, if r<n−r
If so, this is done in preparation for the calculation based on equation (3). The operation code OP of this step is "0111" as shown in FIG. 6, and the operation decoder 15 outputs the signals OF, OS, the subtraction signal _SB , and the judgment signal _JU . Also, at this time, the row designation address signal S _U is sent from the ROM 11.
"100" (4), F _U "101" (2), column address signal S _L
“0000” (0) and F _L “1101” (13) are output.
Therefore, in the same operation as in step Sc above, in this case, the arithmetic circuit 29 performs a subtraction operation by subtracting the content "5" of the A register from the content "7" of the Y register, and the result of the judgment is that there is data. The signal and the carry signal are sent to AND circuits 35 and 36 via OR circuit 33 and line k, respectively. In this example, "7-5=2", that is, r≧n-
From r, only the data presence signal is applied to the AND circuit 35 via the OR circuit 33. At this time, since the judgment signal J _U is applied from the operation decoder 15 to the other input terminal of the AND circuit 35, a “1” signal is output from the AND circuit 35, and the address register 13 is outputted via the OR circuit 41. Supplied to the 1st bit. At this time, the next address signal Na from the ROM 11 is "00101" (5), so even if there is an output from the AND circuit 35, the next address
The contents of the Na signal are read into the address register 13 without being changed, and the process proceeds to the next step _SE . If the content of the Y register is smaller than the content of the A register, that is, if r<n−r, the arithmetic circuit 29 outputs a data present signal and a carry signal, and each of these signals is sent to the AND circuit 35. . I can move on. Therefore, in this embodiment, the address No. 5 is specified as described above, and the process proceeds to step _SE . Next, in step S _E , the content of the A register is "5".
An operation is performed in which the data is transferred to the Z register. The operation code Op in this step _SE is "0100", the operation decoder 15 outputs the signal OS, the timing decoder 16 outputs the read/write signal R/W, and at this time, the ROM 11 specifies the row address. Signal S _U "100"
(4), (A register) F _U "011" (3) (Z register),
Column address signals S _L "000" and F _L "1111" are output, and the contents of the A register are transferred to the Z register by the same operation as in step _SA . At this time, the contents of the address register 13 are changed to "8" from the next address signal Na "01000" (8) of the ROM 11, and the process proceeds to the next step _SF . In the next step S _F , the contents of the B register ``7'' are transferred to the A register by the same operation as in the above step S <sub>E</sub> , and the contents of the address register 13 are changed to ``9''.
, and proceed to step S _G. In this step S _G , the content "5" of the Z register is transferred to the B register by the same operation as in the above step S _E. That is, based on the judgment result of step S _D , the contents of the A register (n-r) and the contents r of the B register are exchanged in steps S _E , S _F , S _G , and the contents of the A register become "7". ”r, the content of the B register becomes “5” (nr). As a result, the state of each register becomes as shown in FIG. 9d. In response to the next address signal Na "00111" (7) of the ROM 11 in step S _G , the process enters the factorial calculation flow () in the next step S _H. A factorial calculation flow is formed by the factorial calculation () in step S _H and the factorial calculation () in step Sj, which will be described later. Then the action is executed. Since the operating procedure shown in FIG. 8 is the same as that of the conventionally known factorial calculation, a detailed explanation of the operation will be omitted here and will be briefly mentioned. First, in the factorial calculation (), step S _H - simply indicates the step in the set state when the factorial calculation is instructed from the key input section.
At 9, some number key is pressed and the value is stored in RAM.
12 of the X register, and then the factorial operation instruction key n1 is operated to set the
A flag indicating the factorial operation is written in the 14th digit. However, in this embodiment, the operation corresponding to this step has already been completed by step _SG . Step SH- is entered, and it is determined whether the value in the X register, that is, the first value n, is a positive integer or not. If "No", the error routine processing is immediately entered and an error is displayed.
If “Yes”, proceed to the next step S _H -. In this case, since n=12, it is judged as ``YES'' (a positive integer), and the process proceeds to step S <sub>H</sub> -, where a numerical value ``1'' is written in the Y register. This is a step to prepare for the actual factorial operations n, (n-1), (n-2), etc. to be multiplied sequentially from the higher numerical terms. When this step S _H - is completed, the present invention skips the single factorial operation flow, changes the contents of the address register 13 to "01011" (11), and proceeds to step S _I in FIG. 7. In step S _I , a step provided for the present invention, it is determined whether the contents of the flag code F stored in the 14th digit of the X register are a combinational operation instruction flag or a factorial operation instruction flag. . That is, in this step, the operation code "1011" is output, and the operation decoder 15 outputs the signals OS, M, the subtraction signal S _B , and the judgment signal J.
A signal _U is output from the timing decoder 16, and a signal CI is output from the timing decoder 16. At this time, the ROM 11 simultaneously outputs the row address signal F _U "001" (1), the column address signal F _L "1110" (14), and outputs the numerical code signal C ₀ "1100". Ru. Then, by the same operation as in step S _D , the contents of the 14th digit of the
Gate circuit G ₇ , latch circuit 28, gate circuit G ₁₀
At the same time, the code signal C ₀ "12" is supplied to the terminal a of the arithmetic circuit 29 via the gate G ₁₂ , and the arithmetic circuit 29 calculates the result according to both input data. Subtraction is executed, and the operation of the subtraction jack is performed based on the result of the operation. When the judgment is "N _O ", that is, the factorial operation instruction flag is determined, step S of the factorial operation () in Fig. 8 is executed. Proceed to _J - _I , and if the answer is ``YES'', proceed to step S <sub>K.</sub> In this embodiment, the arithmetic circuit 2
9 The subtraction “12-12=0” is executed, and the data is also
Since no borrow signal is output, the determination is ``YES'', the contents of the address register 13 are changed to ``12'', and the process proceeds to the next step <sub>SK</sub> . In the next step <sub>SK</sub> , it is determined whether the contents of the X register and the contents of the A register match. This determines the end of the operation of the numerator expression of the combinational operation nCr, that is, n(n-1)・(n-2)...
...(n-r+1) or n・(n-1)・(n-
2) This is for determining whether the calculation of (r+1) has been completed or not. In this step, "0111" is output as the operation code Op, and the operation decoder 1
5 outputs signals SB, OS, OF, and JU. At this time, the signals S <sub>U</sub> “100” and F
<sub>U</sub> “001”, S <sub>L</sub> “0011”, and F <sub>L</sub> “1101” are output. As a result, the arithmetic circuit 29 performs subtraction of "X-A", and if the result is 0, that is, the arithmetic circuit 29 does not output a borrow signal or a data present signal, the contents of both registers match. It is assumed that the above calculation has been completed, and the process goes to step S.
Proceed to <sub>L</sub> , and the above result is not "0", i.e.
When a data presence signal is outputted via the arithmetic circuit 29 and the OR circuit 33, it is assumed that the contents of both registers do not match, and step S of the above-mentioned arithmetic execution is performed.
Proceed to <sub>J</sub> - (factorial operation in Figure 8). In this case, since "12-7=5", it is assumed that the contents of both registers do not match, and the process proceeds to the next step S <sub>I.</sub> Next, in step S <sub>j</sub> -, the contents of the Y register and the contents of the X register are multiplied, and the result is
An operation is performed that writes to a register. That is, in this case nPr=n(n-2)(n-2)...(n-r
+1), first of all “n×1=n” (12×1=
12) The calculation is performed, and as a result, "12" is written to the Y register. Next, the program proceeds to step <sub>SJ--</sub> , in which an operation is performed to subtract a numerical value "1" from the contents of the X register. The operation of this step is ROM1
The operation is almost the same as step Sc, except that the specified signal of the operation code register output from 1 and the code signal Co are different. ] is executed and the result is ``11''.
is written to the X register, resulting in the state shown in FIG. 9e. Then, proceed again to step S _I in Fig. 7. In this step S _I , by the above-mentioned operation, it is determined whether the combinational operation is flagged, and
Proceeding to step S _K , the content of the X register is "11" and the content of the A register is "7" at this step, so it is judged as "NO", and then step S _J -
Then, the contents of the X register "11" are multiplied by the contents of the Y register "12", and the result is written to the Y register. That is, n・(n-1)・(n
-2)...n×(n- of (n-r+1))
The operation 1) is performed, and as a result "132" is written to the Y register. After that, step S _J -
is executed, and further steps S _I →S _K →S _J
- is executed, n×(n-1)・(n-
2)=12×11×10 calculations are performed. Furthermore, repetition of the operation of the above step cycle is performed in step S.
This process is repeated until _G determines that the contents of the X register and the contents of the A register match. That is, the process is repeated until the content of the X register becomes "7".
If a match is found in this step S _K , the calculation of the numerator of the above equation (2) (12×11×10×9×8) = 95040 is completed, and the contents of the address register 13 are changed to “010000” (16 ) and proceed to the next step S _L. The state of the register at this time is as shown in FIG. 9(f). The program advances to the next step S _L , in which the flag code (combination operation instruction code) in the 14th digit of the X register and the B register is cleared. That is, the 14th digit of the X register or B register is specified by the row address signal F _U and the column address signal F _L , the operation coder 15 outputs the signal M, the timing decoder 16 outputs the signal R/W, An operation is performed to write "0" into the 14th digit of both registers. Furthermore, the fourth
In the figure, only the microinstruction to write "0" to the 14th digit of the X register is shown, and the 14th digit of the B register is
Since the microinstruction for specifying the digit differs only in the register specification signal, that step is omitted here. The state diagram of each register at this time is as shown in FIG. 9g. Next, the process proceeds to step _SM , and in this step, the content "5" [(n-r)] stored in the B register in step S _G is transferred to the X register in the same manner as in step F, and the content is transferred to the It will be as follows. Then, the program proceeds to step S _N , and in the same manner as step B, the contents of the Y register, ie, the result of the above factorial operation "95040" is transferred to the B register and temporarily stored, resulting in the result as shown in FIG. 9i. Next, proceed to step S _O and repeat step S _M
Then, a factorial operation (operation for determining the denominator of the above-mentioned formula (3)) of the numerical value (n-r) transferred to the X register is executed. Now, in this case, since X = "5", the steps S _H -, S _H -, S _H -,
The factorial operation flow by S _H -, S _H - changes the contents of the X register "5" to "0" at step S _H -
The calculation is repeated until X ₁ =5×4×3×2×1=120 is obtained, and Y
stored in a register. (FIG. 9i) Then, the program proceeds to step Sp, where the contents of the B register "95040" are transferred to the X register, resulting in the state shown in FIG. 9J. Then, proceed to step S _Q and
The operation of dividing the register content "95040" by the Y register content "120", that is, the operation of dividing the numerator by the denominator of equation (2) of the combinational operation nCr, is executed.
The calculation result "792" is written to the X register. When the result of the combinational operation is obtained in this way, the result is displayed in step S _S after passing through step S _R of post-processing for display. In addition, in the above configuration example, when calculating the combination operation ₈₀ C ₇₈ , the content of _the Y register "78" (numeric value r) and the content of the A register "2" (n-r) are Based on the size judgment, r≧(n-r)
It is determined that this is the case, and the calculation of equation (2) above is executed. That is, through step operations similar to those described above, 80×79=6320 is obtained in steps S _H to S _K of the factorial calculation,
At step _S0 , (n-r)1=21=2 is obtained, and at step Sa, the result of the calculation, ₈₀ C ₇₈ =3160, is obtained and displayed. In this way, in conventional computers, even combinational operations that would result in overflow can be executed and displayed. In the above embodiment, numerical values are stored in the register in an exponential format, but it is of course possible to use other storage formats. As detailed above, according to the present invention, by skillfully utilizing the factorial operation flow and adding a simple judgment means to the conventional one, if the result of the combination operation nCr is a value within the number of digits that can be displayed. For example, the calculation result can be reliably obtained, the input range of input data (numeric values n, r) is expanded, the calculation function is improved, and a calculator that is extremely convenient to use can be obtained. Furthermore, the number of times of factorial calculations is also controlled so that the calculations are not completed until the end and are stopped midway depending on the judgment result, thereby providing a compact electronic calculator that can significantly improve the calculation speed.

[Brief explanation of the drawing]

The drawings show one embodiment of the invention.
2 is a diagram showing the configuration of the present invention, FIG. 2 is a diagram showing the timing pulses used in FIG. 1, FIG. 3 is a diagram showing the configuration contents of the register in the RAM in FIG. Figure 5 is a diagram showing a configuration example of a part of the ROM, operation decoder, and timing decoder section in Figure 5. Figure 5 is a diagram showing the relationship between the main operation code Op and various signals output at that time. Figure 6 is A diagram showing the relationship between the address address at each step and the various signals output at that time, FIG. 7 is a flowchart showing the processing of the combinational calculation, and FIG. 8 is a flowchart showing the processing of the factorial calculation in FIG. 7. , FIG. 9 is a diagram showing changes in the data storage state of registers during combinatorial arithmetic processing. 11...ROM, 12...RAM, 14...
ROM address section, 15...operation decoder, 16...timing decoder, 20...counter, 21...matching circuit, 39...key input section.

Claims (1)

[Claims] 1. A key for specifying a combinational operation (nCr), first and second storage means for storing numerical data input before and after this key as numerical values n and r, respectively; -r), a third storage means for storing the numerical value (n-r) calculated by the calculating means, and a magnitude relationship between the numerical value r and the numerical value (n-r). a determining means for determining, and when the determining means determines that the numerical value r is greater than the numerical value (n-r), exchanging the contents of the second storage means and the contents of the third storage means; exchange means, and the first and second
1. A small electronic calculator characterized by comprising: calculation means for executing nCr calculation based on each numerical value stored in the storage means.