JPS6142184Y2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a computer microprogram control device that processes various operations using microinstructions.

Electronic computers generally employ the microprogram method, but recently, the microprogram method has also come to be used in electronic desktop calculators. The above microprogram method stores a microprogram in a storage device such as a ROM (read only memory),
This is a microprogram control method in which ROM addresses are sequentially specified and microinstructions are read out, and arithmetic operations are performed using these microinstructions.Each address is an address that indicates the address of the next microinstruction stored together with the microinstruction. Information, i.e.
The addresses are designated sequentially by the next address information.

However, if the next address of the ROM is specified only by the address information stored in the ROM as in the above-mentioned conventional method, the next address information of the number of bits sufficient to represent the maximum number of steps will be stored in the ROM. required and takes up a considerable amount of storage space. In addition, conventionally, when performing a jump operation during calculation, that is, when distributing processing to different routines depending on the calculation content,
A judgment circuit is provided separately from the ROM to judge the contents of the upper 1 to 2 bits of the next address, and a jump operation is performed based on the judgment result.
For this reason, there was a problem that the number of steps during jump was large.

The present invention has been made in view of the above points, and provides a microprogram control device that can reduce the area in which address information is stored in a microprogram storage device, and can reliably perform jump operations with a small number of steps. The purpose is to

An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, reference numeral 11 denotes an arithmetic unit, which includes an addition/subtraction circuit 12 that performs addition/subtraction operations, an arithmetic register consisting of, for example, a 16-digit (one digit consists of 4 bits) serial shift register, which stores operation data or results; Y, Z register 13
~15, gate circuits 16 and 17 for controlling input/output of these registers 13 to 15; an OR circuit 18 connecting gate circuit 17 and addition/subtraction circuit 12; It consists of an AND circuit 19. On the other hand, 20 is a storage device such as a ROM (read only memory) that stores a microprogram, and the address is specified by 8-bit address information. The ROM 20 contains microinstructions as well as the lower 4 of the 8-bit address information.
Bit address information is stored in the register 21a that stores the lower 4 bits of the address register 21 by a clock pulse φ generated just before the end of each microinstruction step.
It is set under the control of _e . Also, register 2 stores the upper 4 bits of address register 21.
1b, information of any one of the most significant digits of the shift registers 13 to 15 is read out bit-serially and sent to a 3-bit register 22 via an addition/subtraction circuit 12.
It is controlled and set by a read signal output from an AND circuit 23 to which the clock pulse φ _e is parallel-converted by the AND circuit 23 and input to one side. Then, the 8-bit information set in the address register 21 is controlled by the clock pulse _φ2 ,
The address information is sent to the ROM 20, and the microinstruction and 4-bit address information for the next address are read from the ROM 20 by the address designation. This 4-bit address information is sent to the address register 21 as described above.
Furthermore, microinstructions read from the ROM 20 are sent to the control circuit 24 and decoder 25. The control circuit 24 controls the arithmetic unit 11 according to microinstructions given from the ROM 20. When the decoder 25 receives a jump instruction among the microinstructions read from the ROM 20, it decodes it and outputs a "1" signal. The output signal of this decoder 25 is sent to the AND circuit 23 as a gate control signal. The X and Y registers 13 and 14 are registers for calculations, and the Z register 15 is a _register for storing calculation results. Control information to be displayed, such as overflow, after number setting, after function, print on/off, key switch
A 4-bit code for off, etc. is entered.

Next, the operation of the present invention configured as described above will be explained. Initially, the contents of the upper 4 bits of the address register 21 are all "0", and the address of the ROM 20 is read from the ROM 20, and the contents of the upper 4 bits of the address register 21 are all "0".
1a, it is set under the control of the clock pulse _φe , and is set again under the control of the clock pulse _φ2 .
It is determined by address information A ₁ to _{A 4} supplied to the ROM 20 as address information of the lower 4 bits. That is, address designation is performed using 8-bit information "0000A ₁ A ₂ A ₃ A ₄ " in which address information A ₁ to A ₄ is added to the upper 4 bits of "0". The upper bits below are “0000”
Address information A ₁ ~ in the address block of
An address is specified according to _A4 , and the microinstruction within the specified address is read from the ROM 20 and sent to the control circuit 24, where the arithmetic unit 11 is controlled. Further, during the above arithmetic operation, the contents of the addition/subtraction circuit 12 are always transmitted to the 4-bit register 22. However, during the above calculation, ROM20
When a jump instruction, for example, ``Jump according to the contents of the most significant digit Z _MSD of the Z register 15'' is read from the Z register, the contents of the Z _MSD (4-bit information) are transferred to the Z register according to this instruction. The data is read out in bit serial form and set in the register 22 for serial-to-parallel conversion via the adder/subtractor 12. At the same time, a "1" signal is output from the decoder 25, the gate of the AND circuit 23 is opened, and the clock pulse φ is output. The contents of the register 22, _ie , 3 bits, and the output of the adder/subtractor ₁₂ , ie, the remaining 1 bit of the 4 bits mentioned above, are simultaneously transferred to the upper 4 bits of the address register 21 under the control of the address register 22 and the clock pulse φ2. Therefore, the contents of the upper 4 bits of the address register 21 change from all "0" to the contents of Z _MSD , and jump to the address block specified by Z _MSD . For example, if the content of Z _MSD is "1001", the content of address register 21 is "1001A ₁ A ₂ A ₃ A ₄ "
According to this content, the address of the ROM 20 is specified. That is, an address block is designated by Z _MSD , and individual addresses within this address block are designated by address information A ₁ -A ₄ read from ROM 20.

An example of calculation will be explained below with reference to FIG. When the previous arithmetic operation is completed, the address "00000100" of the ROM 20 is designated as shown in step a, and preparation is made for the next key input operation. When a key is operated in this state, the ROM is
The address "00000010" in step b is determined by the address information "0010" read from 20.
is specified and "Enter the key code to X _MSD "
This command is read out, and the key code is set to the most significant digit of the X register 13. Also, at this time
The next address information "0011" is read from the ROM 20, and the address of step c is designated. The command within this address is "Jump according to the contents of Z _MSD ", and the next address information is "0001".

Since the Z _MSD contains a 4-bit code which is control information indicating the internal state of the computer based on the state of the calculation results up to that point, the jump destination is determined based on the contents. For example, the content of Z _MSD is "0000"
(Print off after function), the address specification is "00000001" and first the Y register 14 is cleared as shown in step _d1 .
Hereinafter, in the address block "0000", an address is designated according to address information _A1 to _A4 , and an arithmetic operation is executed according to the contents of the designated address. Also, if the content of Z _MSD is "0001" (print off after setting), the address specification is "00010001" and first, as shown in step e ₁ , press Y.
A carry is carried out in the register 14, and the arithmetic operation in that address block is subsequently executed. Then, if the content of Z _MSD is "0010" (after overflow), the address specification is "00100001", and as shown in step f, clear _{the X MSD and}
The instruction to jump is executed according to the contents of the jump address, the jump address becomes "00001000", and step _d3 in the address block "0000" is executed.
Jump to. Also, the content of Z _MSD is "1001"
(Print on after setting), the address specification is "10010001", and as shown in step g, X _MSD +
An operation is performed in which 1000 is added and the result of the addition is placed in X _MSD , and then arithmetic operations in that address block are executed. In this way Z
A jump operation is performed according to the contents of _{the MSD} .

According to the above embodiment, when a jump instruction is issued, the state Z is set according to the result of the operation.
Since the jump operation is performed by changing the contents of the upper few bits of the address register 21 according to the contents of _{the MSD} , the jump operation can be performed reliably in one step, and there is no need to add any circuits. Processing routines can be reliably classified with a small number of steps. For example, if the contents of the upper 4 bits of the address register 21 are changed to perform a jump operation, classification of up to 16 types can be performed in one step, and processing speed can be improved.

FIG. 3 shows another embodiment of the present invention, in which the address register 21 and ROM
A decoder 31 is provided between the address register 20 and the address register 20, and the output of the decoder 31 is applied together with the clock pulse φ _e to the register 21b of the upper 4 bits of the address register 21 via the AND circuit 32. 2
Controls information transfer to 1. The decoder 31 detects that the lower 4 bits of address information _A1 to _A4 read from the ROM 20 have reached the highest address, opens the gate of the AND circuit 32, and performs addition/subtraction with the contents of the register 22, that is, the 3 bits. The output signal from the circuit is sent to address register 2 at the same time.
The address information of the upper 4 bits of 1 is read into the register 21b to perform a jump operation.

In the embodiment shown in FIG. 3 as well, the jump operation can be performed in one step as in the previous embodiment.

As described above, the present invention specifies the lower bits of a specified address for a microprogram using address information stored in a storage device, and the upper bits using information stored in a specific digit of a register inside an operation. Therefore, it is possible to provide a microprogram control device that can reduce the area for storing address information in the microprogram storage device and can reliably perform a jump operation in one step.

[Brief explanation of the drawing]

Fig. 1 is a configuration diagram showing one embodiment of the present invention;
The figure is a flowchart for explaining the operation of the same embodiment, and FIG. 3 is a configuration diagram showing another embodiment of the present invention. 11... Arithmetic unit, 12... Addition/subtraction circuit, 13~
15...Shift register, 16, 17...Gate circuit, 20...Memory device (ROM), 21...Address register.

Claims (1)

[Claims for Utility Model Registration] In order to execute various operations step by step using microinstructions, the microinstructions at the corresponding addresses in the fixed storage device are sequentially read out while changing the address information in the address register, and the microinstructions are In a microprogram control device in which a predetermined operation is mainly executed in an arithmetic section based on the above-mentioned information, an upper address section that stores upper address bit information of the address information and one of the microinstructions output from the fixed storage device are used. an address register divided into a lower address part for storing address information; a means for decoding that the step being executed by the currently read microinstruction is a judgment step and outputting a judgment signal; and a means for outputting a judgment signal. Controlled by the signal, the above upper address part is
A gate means for outputting a read signal for reading the upper address bit information, a jump destination address register for storing jump destination address information in a pre-designated digit in the arithmetic unit, and a jump destination address register for storing jump destination address information in a predetermined digit in the arithmetic unit, which is output for each microinstruction. Means for writing address information outputted from the fixed storage device into the lower address field of the address register in response to a clock pulse; and means for reading out the address information stored in the jump destination address register and outputting it from the gate means when decoding the judgment step. A microprogram control device comprising means for storing data in the upper address section in synchronization with the writing means within an execution cycle of the judgment step under the control of a read signal from the above.